FPGA/VHDL Matrix Multiply

[fiofury1]

I have been assigned the task of implementing a filter that utilizes the following update equation in MATLAB:

P = (1 / lambda) * (P - ((P * u * u' * P) / (lambda + u' * P * u)));

In this equation, ‘P’ is a [5x5] matrix, ‘u’ is a [5x1] matrix, and ‘lambda’ is a constant. P must be computed every 10uS (100kHz), and the implementation can utilized either fixed-point or floating point numbers. Can anyone give me any suggestions as to how to implement this equation in VHDL. I am using an Altera Dev. Board with a Startix II EP2S60 FPGA. I have attempted instantiating a NIOSII processor into the FPGA and running a C program to compute P, but this option was too slow. I also realize that I might have to tough it out and simply expand the equations and “code away” or develop a solution using matrix multiplication modules.

Thanks,

Jon

 

[scottcarl]

Jon,

I've built one of these and there is no other way to do it but slog through all the calculations. Mine was an [8x8] complex matrix, ugh. So for a [5x5]x[5x1] you'll have 25 multiplications with 5 results stored into a [5x1] matrix. However, the u'P multiply is seen twice in your equation and therefore should only calcualate it once, saving some time. Here is the attachment of the rendition of what you should build.

Regards,
Scott