Getting started with VHDL and Verilog

[jraj.thakkar]

Hi all,

My background is in Software Engineering C,C++,Java and Unix. I am
getting started with VHDL and Verilog. What is the good way/books/
websites/training to get started? I have B.S. and M.S. in Computer
Engineering. Also, what is the learning curve in VHDL and Verilog?

Please let me know.

Thanks
Jay

 

[Tricky]

Hi all,

My background is in Software Engineering C,C++,Java and Unix. I am
getting started with VHDL and Verilog. What is the good way/books/
websites/training to get started? I have B.S. and M.S. in Computer
Engineering. Also, what is the learning curve in VHDL and Verilog?

Please let me know.

Thanks
Jay

First thing to do is to get fully immersed in digital electronics.
Trying to write VHDL or verilog from a software approach will only
lead to failure. These are not programming language, they are
description languages. There is some cross-over, but for synthesizable
code you cannot write like a programmer.

Theres a nice web-page with all the basic gates, register types and
much more explained and demostrated (via a great JAVA interface) at
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/00-intro/00-welcome/chapter.html

 

[Mike Treseler]

... for synthesizable
code you cannot write like a programmer.

I can write a synthesis *process* like a programmer,
http://mysite.verizon.net/miketreseler/stack.vhd
but I can't wire them together like a programmer.

Theres a nice web-page with all the basic gates, register types and
much more explained and demostrated (via a great JAVA interface) at
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/00-intro/00-welcome/chapter.html

Nice digital demo. Thanks.

-- Mike Treseler