how can I use a signal defined in one Architecture to another Architecture

Discussion in 'VHDL' started by Muhammad Khan, Jul 9, 2003.

  1. Hello everybody,

    I want to use the signal defined in one architecture in VHDL to
    another architecture. I have two architecture in the same .vhd file
    and I am using Component mapping. I required the result of calculation
    of a signal to be used in second architecture. Can any one tell how to
    defined signal so that it is globally visible to other architectures.

    Regards

    Khan
     
    Muhammad Khan, Jul 9, 2003
    #1
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  2. Muhammad Khan

    Mario Trams Guest

    Hello Muhammad,

    this is a common question.

    The clean way for handling this is to feed the signal through
    the port maps.

    Regards,
    Mario

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    Mario Trams, Jul 9, 2003
    #2
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  3. Muhammad Khan

    Jon Guest

    Hi Khan,
    If you declare a signal in a package and you include the package
    then the signal can be globally used by all architectures that
    reference that package. This is for simulation only and will not
    work for synthesis.

    Jon
     
    Jon, Jul 9, 2003
    #3
  4. Muhammad Khan

    Ken McElvain Guest


    This will work for synthesis in Synplify Pro 7.3.
     
    Ken McElvain, Jul 10, 2003
    #4
  5. Cool. Never seen that in synthesis before.
    How did you get test cases?

    -- Mike Treseler
     
    Mike Treseler, Jul 10, 2003
    #5
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