how to avoidind multisourcing on signal

Discussion in 'VHDL' started by yogesh malekar, Apr 5, 2014.

  1. How to avoi multisourcing on the signal,and bad synchronois descrption
     
    yogesh malekar, Apr 5, 2014
    #1
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  2. Anybody give me vhdl program for non restoring division algorithm
    To burn it on cpld working on 4 MHZ
    frequency
     
    yogesh malekar, Apr 5, 2014
    #2
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  3. yogesh malekar

    KJ Guest

    Perhaps by asking someone other than you to write the code.
     
    KJ, Apr 5, 2014
    #3
  4. Am Samstag, 5. April 2014 21:20:15 UTC+2 schrieb yogesh malekar:
    The best way is avoid it during code writing. Second best solution is to detect such issues as fast as possible.

    Multisourcing can be detected during compile of code, if you use no resolved signal types (only std_ulogic or std_ulogic_vector).
    So if you use only unresolved type you know if code can be simulated, it has no multisourcing at all.

    For bad synchronous description you could identify all clock domain crosings (CDC) by hand and verify their correct handling. Alternative spend money in license for tools to help in identifying and verifying of CDC.

    regards Thomas
     
    Thomas Stanka, Apr 7, 2014
    #4
  5. yogesh malekar

    GaborSzakacs Guest

    "multi-source" happens when you drive (assign) a signal in more than
    one process. Don't do that for synthesis.

    "bad synchronous description" is a term used by Xilinx to tell you that
    your sequential logic does not match a standard flip-flop template. To
    avoid that use the language templates to see what the synthesis tools
    expect. For xilinx this is available in the GUI (light bulb icon) as
    well as in the XST user guide.
     
    GaborSzakacs, Apr 7, 2014
    #5
  6. yogesh malekar

    Daniel Kho Guest

    Yes, like Gabor said, "multi-source" is a term used when you have multiple drivers to a signal. If you don't intend to have multiple sources for a signal (which is the case for most designs), I recommend the use of the unresolved VHDL types, such as std_ulogic, std_ulogic_vector, or unresolved_unsigned. By declaring signals to be unresolved, and if you accidentally drive them from multiple sources, your simulator must give you an error.

    OTOH, if you use resolved types, your simulator will automatically resolve the value of the signal as a function of all the input drivers (resolution function).

    However, most synthesis tools (those that I know of) don't honour this though. They still give you an error even for a resolved signal and doesn't automatically resolve the signal based on some function of its inputs. But simulators are very strict in this sense.

    -daniel
     
    Daniel Kho, Apr 8, 2014
    #6
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