How To Control The Z Modeling In Lec(formal Verification Tool)??

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Hi
Actually when I am doing Equivalence checking, between RTL and NL, the LEC TOOL is modeling a MUX(z-modeling) for many pins. But sometimes, even if pin is not floating it inserts a mux before a pin, whose 2nd i/p pin is floating. So I can say that z-modeling in LEC is unpredictable. Can any one tell me, how to control this unpredictability???

With Rgds.
Subhash Jha
 
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