How to model a buffer in VHDL

[vishallko31]

Hi
Im trying to model a buffer in VHDL but am unable to do so...

I have a signal A and I want to generate a signal B which is nothing
but A delayed by 2 seconds.

i.e B <= A after 2 ns;


But the above way does not work as I do not see anything on B.

When A (widht of A) is high for 1ns , then B is 0 but if I increase the
width of A to 3ns then I am able to see B with a delay of 2 ns

Please suggest some way

 

[abilashreddyg]

This is because of the default ineretial delay of vhdl.To see your
required behaviour replace the inertial delay with transport delay.

b<= transport a after 20 ns;

Thanks,
Abilash.

 

[vishallko31]

Thanks Abilash
This is working now....
but I dont understand why it wasnt working in the first case

 

[Ralf Hildebrandt]

Im trying to model a buffer in VHDL but am unable to do so...

I have a signal A and I want to generate a signal B which is nothing
but A delayed by 2 seconds.

i.e B <= A after 2 ns;

But the above way does not work as I do not see anything on B.

If you want to model synthesizable hardware no kind of delay will work.
How do you think a delay can be implemented in real hardware?

A buffer is nothing more that a simple flipflop. If you don't seek for a
buffer but for a delay element, you may use a 500MHz clock (2ns) and
buffer your signal in the flipflop. But I strongly recommend to think
about another solution. If you need fixed delay you did probably
something wrong.

Ralf

 

[KJ]

but I dont understand why it wasnt working in the first case

In the first case you assigned a new value to the signal before the
first value had 'made it through'. VHDL assignments default to what is
called 'inertial mode' which means that if you assign a value to some
signal and then later assign it again the first assignment, if it
hasn't yet occurred, is essentially discarded. Your first example was

B <= A after 2 ns;
A <= '1', '0' after 1 ns;

Because 'A' changed to '1', the simulator scheduled for the signal 'B'
to be changed 2 ns later. But then 1 ns later 'A' changed back to '0'
so the simulator cancelled the earlier assignment of 'B' and scheduled
the new assignment to happen 2 ns later (at t = 3 ns).

When you put the keyword transport in this 'cancelling of previously
scheduled assignments' does not occur.

B <= transport A after 2 ns;
A <= '1', '0' after 1 ns;

Works as you expected. VHDL gives you the option (via the 'transport'
keyword) of how you want to handle multiple scheduled assignments. Up
to you to decide which is appropriate for your application.

KJ

 

[vishallko31]

Hi Kj and Ralf
thanks a lot for the advice...Understood....

Thanks once again
Regards
Vishal

 

[KJ]

If you want to model synthesizable hardware no kind of delay will work.

How do you think a delay can be implemented in real hardware?

Read the post, it said nothing about synthesizable hardware, just that
he wanted to model a 2ns delay buffer.

A buffer is nothing more that a simple flipflop

No, a simple flip flop is not at all like a buffer.

If you don't seek for a
buffer but for a delay element, you may use a 500MHz clock (2ns) and
buffer your signal in the flipflop. But I strongly recommend to think
about another solution. If you need fixed delay you did probably
something wrong.

Perhaps you should re-read the original post and the question that was
actually posed.

KJ