How to "or" a generic array of std_logic_vector ?

[HansWernerMarschke]

I have an array of std_logic_vector.

type array_of_std_logic_vector is array (0 to
number_of_rotors_array-1) of std_logic_vector(0 to
data_width_array-1);
signal data_out_array : array_of_std_logic_vector;

I want to "or" the "bits" of std_logic_vector for each element of the
vector like this.
data_out(i) shall be '1' if one of the elements of the vector has set
this bit to one.

data_out(0) <= '1' when unsigned(data_out_array(0)) /= 0;
data_out(1) <= '1' when unsigned(data_out_array(1)) /= 0;

The problem is that number_of_rotors and although data_width_array are
generic.

So, what is the solution ?

Thank´s for help

 

[HansWernerMarschke]

Thank´s for help

For a single std_logic_vector this is no problem.

error <= '1' when unsigned(error_array) /= 0 else '0';
restart <= '1' when unsigned(restart_array) /= 0 else '0';

I´ve tried to solve the problem by using the following process:

process (data_out_array)
begin
for j in 0 to data_width_array - 1 loop
for i in 0 to number_of_rotors_array - 1 loop
if data_out_array(i)(j) = '1'
then
temp_data_out(j) <= '1';
else
null;
end if;
end loop;
data_out(j) <= temp_data_out(j);
end loop;
end process;

But there are still some latches.
Now I have a component named LDP in the design.
The synthesis says that some signals are missed in the sensitivity
list.
What about using a resolution function like this for example ?

-- function wired_or (inputs: bit_vector) return bit is
-- constant float_value: bit := '0';
-- begin
-- if inputs'length = 0 then
-- return float_value;
-- else
-- for i in inputs'range loop
-- if inputs(i) = '1' then
-- return '1';
-- end if;
-- end loop;
-- return '0';
-- end if;
-- end function wired_or;

-- subtype bus_bit is wired_or bit;
-- signal a : bus_bit;

 

[Mike Treseler]

But there are still some latches.

Using a synchronous process would eliminate the latches.

-- Mike Treseler

 

[HansWernerMarschke]

Thank´s for your help

I know now that using something like this:

error <= '1' when unsigned(error_array) /= 0 else '0';
restart <= '1' when unsigned(restart_array) /= 0 else '0';

... is not a good idea.
Instead you have to use a process like this:

process (error_array)
variable temp_error : std_logic;
begin
temp_error := '0';
for i in error_array'range loop
temp_error := temp_error or error_array(i);
end loop;
error <= temp_error;
end process;

... then a OR is generated.
For the OR of the bits of the array of std_logic_vector I use this;
although I don´t understand that not an OR gate is generated. Instead
of this I get a sequence of OR´s and AND´s where one input is negated.
It´s a pitty that I can´t show the scheme that is generated.

process (data_out_array)
variable temp_data_out : std_logic_vector(0 to data_width_array -
1);
begin
for i in 0 to data_width_array - 1 loop
temp_data_out(i) := '0';
for j in 0 to number_of_rotors_array - 1 loop
if data_out_array(j)(i) = '1'
then
temp_data_out(i) := '1';
else
null;
end if;
end loop;
data_out(i) <= temp_data_out(i);
end loop;
end process;

 

[KJ]

I want to "or" the "bits" of std_logic_vector for each element of the
vector like this.
data_out(i) shall be '1' if one of the elements of the vector has set
this bit to one.

Somewhat similar to the process approach already covered in this thread is
to use a generate statement...basically the same amount of typing and debug

Gen_This : for i in data_out'range generate
data_out(i) <= '1' when unsigned(data_out_array(i)) /= 0;
end generate Gen_This;

KJ

 

[Andy]

Somewhat similar to the process approach already covered in this thread is
to use a generate statement...basically the same amount of typing and debug

Gen_This : for i in data_out'range generate
data_out(i) <= '1' when unsigned(data_out_array(i)) /= 0;
end generate Gen_This;

KJ

The problem (latches) with this solution as well as that in the OP is
that there is no assignment to data_out when the row is 0.

Try:

data_out(i) <= '1' when unsigned(data_out_array(i)) /= 0 else '0';

Other than my personal preference to avoid combinatorial processes
(either explicit or implied by concurrent assignments), I see nothing
wrong with using the generate statement, so long as the concurrent
statements within it do not create latches. In fact, I prefer a
concurrent assignment statement over a combinatorial process that has
only one output.

Andy

 

[KJ]

The problem (latches) with this solution as well as that in the OP is
that there is no assignment to data_out when the row is 0.

Try:

  data_out(i) <= '1' when unsigned(data_out_array(i)) /= 0 else '0';

That's what I had intended to type...good catch.

KJ