How to stop Infinite loop

[shah_satish2002]

Hi...In my code, Its working good if i run in model sim with debugg but if i select "Run All" then its showing Error.

** Error: (vsim-3601) Iteration limit reached at time 0ps.
This is because of Infinite loop..Can any body tell me how can i stop it at the end of my programme ??

My code is :-


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mem.all;

entity FA_calc is
port( clk : std_logic;
MTmux : inout std_logic_vector(width-2 downto 0);
MTdat : in std_logic_vector(width-2 downto 0);
MTout : out word2;
MTout_analyzer : out std_logic_vector(width-2 downto 0);
load : in std_logic
);
end FA_calc;

architecture behav of FA_calc is
signal sig_mem : word1;
signal sig_out : word3;
--signal cnt1: integer range 0 to 7 ;

--signal counter : std_logic_vector(12 downto 0) := "0000000000000";

--variable cnt : integer range 0 to 6720;

signal clkenable,rst : std_logic;
signal OE : std_logic;


begin

clkdiv : process(clk,MTmux)

variable cnt: integer range 0 to 2 ;
variable cnt1: integer range 0 to 12 ;
variable mtmux_count:integer range 0 to 11;

begin


if clk = '1' and clk'event then

-- if (rst = '0')then

-- cnt1 := 0;

-- end if;

if ( cnt1 = 0) then

MTmux <="000" ;

end if ;

if (OE = '1')then

mtmux_count := mtmux_count + 1;

case mtmux_count is

-- when 0 => MTmux <="000";
when 1 => MTmux <= "001" ;
when 2 => MTmux <= "000" ;
when 3 =>MTmux <= "010" ;
when 4 =>MTmux <= "001" ;
when 5 =>MTmux <= "011" ;
when 6 =>MTmux <= "110" ;
when 7 =>MTmux <= "001" ;
when 8 =>MTmux <= "111" ;
when 9 =>MTmux <= "100" ;
when 10 =>MTmux <= "001" ;
when 11 =>MTmux <= "101" ;
mtmux_count := 0;
-- cnt1 := 0;
when others =>
NULL;
end case;

OE <= '0' ;

end if;

cnt := cnt + 1;

if (cnt = 2) then

cnt1 := cnt1 +1;

OE <= '1' ;

case MTmux is
when "000" =>
sig_mem(0)(width-1 downto 1 ) <= MTdat;
when "001" =>
sig_mem(1)(width-1 downto 1) <= MTdat;
when "010" =>
sig_mem(2)(width-1 downto 1) <= MTdat;
when "011" =>
sig_mem(3)(width-1 downto 1) <= MTdat;
when "100" =>
sig_mem(4)(width-1 downto 1) <= MTdat;
when "101" =>
sig_mem(5)(width-1 downto 1) <= MTdat;
when "110" =>
sig_mem(6)(width-1 downto 1) <= MTdat;

when others =>
NULL;
end case;


cnt := 0;

if (cnt1 = 12) then
cnt1 := 0;
sig_mem(1)(0) <= load;
OE <= '0' ;
--cnt1 := '0';
-- sig_mem(0)(0) <= '0';
clkenable <= '0';
end if;


end if;
end if;
end process;


ld : process(clkenable,sig_mem,sig_out)

variable cnt2: integer range 1 to 15 ;

begin

if clkenable ='0' then

MTout_analyzer <= sig_mem(0)(3 downto 1);
sig_mem(2)(0) <= sig_out(1)(0);
sig_mem(3)(0) <= sig_out(2)(0);
sig_mem(4)(0) <= sig_out(3)(0);
sig_mem(5)(0) <= sig_out(4)(0);
sig_mem(6)(0) <= sig_out(5)(0);
--sig_mem(7)(0) <= sig_out(6)(2);

MTout(12) <= sig_out(1)(2);
MTout(11) <= sig_out(1)(1);
MTout(10) <= sig_out(2)(2);
MTout(9) <= sig_out(2)(1);
MTout(8) <= sig_out(3)(2);
MTout(7) <= sig_out(3)(1);
MTout(6) <= sig_out(4)(2);
MTout(5) <= sig_out(4)(1);
MTout(4) <= sig_out(5)(2);
MTout(3) <= sig_out(5)(1);
MTout(2) <= sig_out(6)(2);
MTout(1) <= sig_out(6)(1);
MTout(0) <= sig_out(6)(0);
cnt2 := cnt2 + 1;

-- if (cnt2 = 13) then

-- rst <= '0' ;

-- end if ;

end if;


end process ld;


ld1 : process(sig_mem)
--variable cnt2: integer range 0 to 7 ;

begin

if clkenable ='0' then

for i in 1 to 6 loop

case sig_mem(i) is
when "0000" =>
sig_out(i)(width-2 downto 0 ) <= "000";

when "0010" =>
sig_out(i)(width-2 downto 0) <= "000";

when "0011" =>
sig_out(i)(width-2 downto 0) <= "100";

when "0111" =>
sig_out(i)(width-2 downto 0) <= "100";

when "0110" =>
sig_out(i)(width-2 downto 0) <= "110";

when "0100" =>
sig_out(i)(width-2 downto 0) <= "110";

when "0101" =>
sig_out(i)(width-2 downto 0) <= "010";

when "1101" =>
sig_out(i)(width-2 downto 0) <= "010";

when "1100" =>
sig_out(i)(width-2 downto 0) <= "011";

when "1110" =>
sig_out(i)(width-2 downto 0) <= "011";

when "1111" =>
sig_out(i)(width-2 downto 0) <= "111";

when "1011" =>
sig_out(i)(width-2 downto 0) <= "111";

when "1010" =>
sig_out(i)(width-2 downto 0) <= "101";

when "1000" =>
sig_out(i)(width-2 downto 0) <= "101";

when "1001" =>
sig_out(i)(width-2 downto 0) <= "001";

when "0001" =>
sig_out(i)(width-2 downto 0) <= "001";

when others =>
NULL;

end case;

end loop;

end if;
end process ld1;


end behav;



Thanks in advance..