Discussion in 'VHDL' started by VIPS, Jun 4, 2009.

  1. VIPS

    VIPS Guest

    Hi All

    I am implementing the I2C Slave and i am using two data lines for sda
    input and sda output.

    MY question is that shall I expect from I2C bus to give me Z as input
    in place of 1

    Shall I drive output 1 as Z to the sda_out

    Secondly We cannot synthesize Z as an input but can drive the output
    as Z any reason

    I have used an interal sda signal and sampled the SDA_input as

    SDA_internal<= '1' when SDA_input = 'Z' else '0' ; it is stucking the
    output /input to gnd and vcc in synthesis

    Pls specify


    VIPS, Jun 4, 2009
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  2. SDA_internal<= '1' when SDA_input = 'Z' else '0' ; it is stucking the
    If you are using a Xilinx device you can use an IO primitive with
    a tristate output. This is the same kind of primitive you would
    use on a memory data bus, for example. The trick is to connect the
    SDA output to the IO Tristate, and connect '0' to the IO Output.
    Then when your SDA output goes low the tristate turns off and drives
    the output to '0'. When your SDA output goes high, the tristate turns
    on and effectivly outputs a 'Z', the '0' at the IO Output is ignored.

    Brad Smallridge
    Brad Smallridge, Jun 5, 2009
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  3. Jonathan Bromley a écrit :

    Does this synthesize ok?
    I stick to the good old tri-state driver (assign 'Z' to the output) and
    add the pull-ups in the constraint file but if the tools can handle this
    syntax I will probably change my ways. Why maintain two files when one
    is enough?

    Nicolas Matringe, Jun 5, 2009
  4. VIPS

    Bert_Paris Guest


    I do things a bit differently :

    1. In the FPGA :
    SDA in inout,
    SDA <= '0' when SDAout ='0' else 'Z';
    Because :
    * most synthesis tools I used at this time did NOT infer
    internal pullups using 'H', you need a constraint on the IO pin.
    * Internal pullups in all technologies I used were way
    too week for the purpose (slew rate too low, -> glitches after input).
    * there should always be an external pull up resistor on the i2c
    signals anyway.

    2. In the FPGA :
    SDA_in <= SDA or SDA;
    (as an alternative to To_X01, which is more academic)

    3. In the FPGA :
    I insert a simple digital filter (especially recommended on SCL).
    This allowed me to have a working system with only an
    internal pull up (not recommended though).

    5. In the _Test bench_ :
    SDA <= 'H';
    to model the external pull up resistor and get an H
    when neither Master nor Slave(s) are driving.

    Most applies to SCL (though the slave won't drive it)

    Hope this helps,

    Bert_Paris, Jun 5, 2009
  5. VIPS

    Stef Guest

    In comp.lang.vhdl,
    That's not entirely correct. A slave may hold SCL low when its is busy and
    releasy it when ready. So a master must always check if SCL has returned
    high before proceeding.
    Stef, Jun 5, 2009
  6. VIPS

    Bert_Paris Guest

    That's not entirely correct. A slave may hold SCL low when its is busy and
    Good remark !
    My slaves were never busy so I coded SCL only as "in".

    Bert_Paris, Jun 6, 2009
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