inout problem

Discussion in 'VHDL' started by csosza3, Apr 11, 2006.

  1. csosza3

    csosza3 Guest


    I made a simple ram model to test inout but the testbench result not as
    I expected.

    If I remove the two last line
    data <= "0011";
    rw <= '0';
    it is ok but if I add them the result is wrong. How can be modified
    this design and the testbench to read and write data in normal way? I'd
    like a simple ram model with working testbench.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity ram is port (
    data : INOUT std_logic_vector( 3 downto 0 );
    rw : IN std_logic );
    end ram;

    architecture arch of ram is
    process (rw)
    variable data_s: std_logic_vector( 3 downto 0 ) := "0000";
    if ( rw = '0') then
    data_s := data;
    elsif ( rw = '1') then
    data <= data_s;
    end if;
    end process;
    end arch;

    library ieee;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_1164.all;

    entity ram_tb is
    end ram_tb;

    architecture TB_ARCHITECTURE of ram_tb is
    component ram
    data : inout std_logic_vector(3 downto 0);
    rw : in std_logic );
    end component;

    signal rw : std_logic;
    signal data : std_logic_vector(3 downto 0);


    UUT : ram
    port map (
    data => data,
    rw => rw

    stm: process
    wait for 300 ns;

    rw <= '1';
    wait for 1300 ns;

    data <= "0011";
    rw <= '0';


    end process;

    csosza3, Apr 11, 2006
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  2. csosza3

    Andy Peters Guest

    Why the std_logic_unsigned?????
    Your problem is that you have two assignments to the same signal
    (data). One assignment is in the RAM and the other's in the test

    You need to tristate the RAM data, just like you'd do if you had a RAM

    The testbench should tristate the data signal when it is doing a RAM

    Similarly, the RAM entity should tristate the data signal when you
    write to the RAM.

    Andy Peters, Apr 12, 2006
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