Is there a way to define different names to same signal in VHDL?

[Eli]

I'm looking for a method to use substitute names to same signal VHDL
so the synthesis tool would use the same flops for all of them.... is
there a way to do it right?

Thanx

 

[Tricky]

I'm looking for a method to use substitute names to same signal VHDL
so the synthesis tool would use the same flops for all of them.... is
there a way to do it right?

Thanx

it should already do this, for example:

signal reg : std_logic;
signal a,b,c : std_logic;

process(clk)
begin
if rising_edge(clk) then
reg <= input;
end if;
end process;

a <= reg;
b <= reg;
c <= reg;

a, b and c are all just a registered version of the input.

similarly, if you do this:

process(clk)
begin
if rising_edge(clk) then
reg1 <= input;
reg2 <= input;
end if;
end process;

a <= reg1;
b <= reg2;
c <= a;

when it is synthesised, it will probably compress reg1 and reg2 into
the same register (unless you specifically tell it not to).

otherwise you can alias signals to avoid the delta delays (in
simulation) from the above methods:

signal reg1 : std_logic;
alias a : std_logic is reg1;

IS this what you wanted?

 

[Eli]

it should already do this, for example:

signal reg : std_logic;
signal a,b,c : std_logic;

process(clk)
begin
  if rising_edge(clk) then
    reg <= input;
  end if;
end process;

a <= reg;
b <= reg;
c <= reg;

a, b and c are all just a registered version of the input.

similarly, if you do this:

process(clk)
begin
  if rising_edge(clk) then
    reg1 <= input;
    reg2 <= input;
  end if;
end process;

a <= reg1;
b <= reg2;
c <= a;

when it is synthesised, it will probably compress reg1 and reg2 into
the same register (unless you specifically tell it not to).

otherwise you can alias signals to avoid the delta delays (in
simulation) from the above methods:

signal reg1 : std_logic;
alias a : std_logic is reg1;

IS this what you wanted?

Thanx, but i'm looking for real substitute, like in C language.
I'll write iot in pseudo-code:

if i have signal defined:
signal generic_register : integer range 0 to 1023l;

and some statements like:
up_counter IS SUBSTITUTE OF generic_register;
down_counter IS SUBSTITUTE OF generic_register;

so i can use statements like

up_counter <= down_counter+1;
and get the result as i wrote generic_register <= generic_register+1;

i'm looking for a nice and readable way to use the same generic signal
or variable which gets completely different meaning

 

[KJ]

Thanx, but i'm looking for real substitute, like in C language.
I'll write iot in pseudo-code:

if i have signal defined:
signal generic_register : integer range 0 to 1023l;

and some statements like:
up_counter IS SUBSTITUTE OF generic_register;
down_counter IS SUBSTITUTE OF generic_register;

so i can use statements like

up_counter <= down_counter+1;
and get the result as i wrote generic_register <= generic_register+1;

i'm looking for a nice and readable way to use the same generic signal
or variable which gets completely different meaning- Hide quoted text -

Look into the 'alias' statement. It does exactly what you're
describing.

KJ

 

[Eli]

Look into the 'alias' statement.  It does exactly what you're
describing.

KJ

looks like this is the solution, thanx.

Are the following statements valid and supported by various synthesis
tools for FPGA?

signal misc_register : integer range 0 to 511; -- general
alias pid_tick_count_value_ALIAS: integer range 0 to 511 IS
misc_register integer range 0 to 511;
alias scan_channel_params_ALIAS: integer range 0 to 31 IS
misc_register integer range 0 to 31;
alias i_buff_remain_values_ALIAS: integer range 0 to 127 IS
misc_register integer range 0 to 127;
alias d_buff_remain_values_ALIAS: integer range 0 to 127 IS
misc_register integer range 0 to 63;

 

[Eli]

Nope, at least not in Quartus.

subtype int512_t is integer range 0 to 511;
signal misc_register : int512_t;
alias pid_tick_count_value_ALIAS : int512_t is misc_register;

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

so if they integer type they must be the same range exactly?
what about std_logic_vector type? may they be partial set of bits like
this?
misc_register : std_logic_vector (15 downto 0);
alias pid_tick_count_value_ALIAS : std_logic_vector (4 downto 0)
misc_register (15 downto 12);

 

[Jonathan Bromley]

so if they integer type they must be the same range exactly?

An alias is exactly that: a different name for the same thing.
So it is no great surprise that the subtype of alias and thing
must be the same.

what about std_logic_vector type? may they be partial set of bits like
this?

Yes, provided you get the length right. In this case the
alias can have a subtype that is different from the thing's,
but the lengths must match so that the alias and the thing
can participate in exactly the same operations. So your
example is flawed:

 

[Eli]

An alias is exactly that: a different name for the same thing.
So it is no great surprise that the subtype of alias and thing
must be the same.


Yes, provided you get the length right.  In this case the
alias can have a subtype that is different from the thing's,
but the lengths must match so that the alias and the thing
can participate in exactly the same operations.  So your
example is flawed:

OK, OK, it was just my mistake. It should be this way:
std_logic_vector (4 downto 0) is misc_register (15 downto 11);

 

[Eli]

An alias is exactly that: a different name for the same thing.
So it is no great surprise that the subtype of alias and thing
must be the same.


Yes, provided you get the length right.  In this case the
alias can have a subtype that is different from the thing's,
but the lengths must match so that the alias and the thing
can participate in exactly the same operations.  So your
example is flawed:

OK, OK, it was just my mistake. It should be this way:
std_logic_vector (4 downto 0) is misc_register (15 downto 11);

 

[Eli]

An alias is exactly that: a different name for the same thing.
So it is no great surprise that the subtype of alias and thing
must be the same.


Yes, provided you get the length right.  In this case the
alias can have a subtype that is different from the thing's,
but the lengths must match so that the alias and the thing
can participate in exactly the same operations.  So your
example is flawed:

my mistake. it should be:
alias pid_tick_count_value_ALIAS : std_logic_vector (4 downto 0) is
misc_register (15 downto 11);