Hello,
I am using Xilinx ISE 10.1 to synthesize some code that simulates correctly. This is my first nontrivial (to me) FPGA/digital design. I am getting the error:
By commenting out clk_counter := clk_counter + 1, the error goes away (although there are different errors that appear).
My full code can be found here.
A Word document explaining what I am trying to do is here. In short, I am trying to build a serial to parallel radio decoder.
What am I doing wrong in the following code?
-- clock/timing process
process(clk)
begin
-- asynchronous reset
if (reset = '1') then
current_state <= reset_st;
elsif rising_edge(clk) then
-- wrapping counter that keeps track of FPGA clocks
clk_counter := clk_counter + 1; -- fail
debug_current_counter <= clk_counter;
-- used for time-outs of polling in the state machine
-- fsm sets bit_poll and three_half_bit_time
if (bit_poll = '1' and clk_counter = three_half_bit_time) then
current_state <= store_bit_st;
else
current_state <= next_state;
end if;
end if;
end process;
Thanks!
Sam
I am using Xilinx ISE 10.1 to synthesize some code that simulates correctly. This is my first nontrivial (to me) FPGA/digital design. I am getting the error:
Multi-source on Integers in Concurrent Assignment.
By commenting out clk_counter := clk_counter + 1, the error goes away (although there are different errors that appear).
My full code can be found here.
A Word document explaining what I am trying to do is here. In short, I am trying to build a serial to parallel radio decoder.
What am I doing wrong in the following code?
-- clock/timing process
process(clk)
begin
-- asynchronous reset
if (reset = '1') then
current_state <= reset_st;
elsif rising_edge(clk) then
-- wrapping counter that keeps track of FPGA clocks
clk_counter := clk_counter + 1; -- fail
debug_current_counter <= clk_counter;
-- used for time-outs of polling in the state machine
-- fsm sets bit_poll and three_half_bit_time
if (bit_poll = '1' and clk_counter = three_half_bit_time) then
current_state <= store_bit_st;
else
current_state <= next_state;
end if;
end if;
end process;
Thanks!
Sam