Multi-source in Unit <calc_module> on signal <disp_out>

[shirodkarrakesh]

Hello I am trying to implement a calculator in VHDL. At the same time I need to display the input numbers and the result on the four unit 7-segment display. The syntax seems to be OK but when i try to synthesize the code it gives me an error.Multi-source in Unit <calc_module> on signal <LEDout<3>>
Could anyone suggest me anything! My code is as below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;



entity calc_module is
Port ( enter,add,sub,mult : in boolean;
clk: in std_logic ;
num: in STD_LOGIC_vector(7 downto 0);
--result: out std_logic_vector(3 downto 0);
LEDout : out STD_LOGIC_VECTOR (6 downto 0);
num1,num2: inout std_logic_vector(7 downto 0);
dec_out: out std_logic_vector(3 downto 0)
);
end calc_module;


architecture Behavioral of calc_module is


signal a,b,c: std_logic_vector(7 downto 0);
shared variable z:integer:=0;
signal dec_in:std_logic_vector(1 downto 0);
signal s:std_logic_vector(2 downto 0);

component
led_decoder port ( i : in std_logic_vector(3 downto 0);
o : out std_logic_vector(6 downto 0));
end component;


begin

process(clk, enter)

end process;


process (clk,add,sub,mult)
begin
if (z=0)then
num1 <= num;
z:=1;
else
num2 <= num;
end if;

if ( clk'event and clk='1') then
case dec_in is
when "00" => dec_out <= "1110";
when "01" => dec_out <= "1101";
when "10" => dec_out <= "1011";
when "11" => dec_out <= "0111";
when others => dec_out<= "1111";
end case;
end if;

a<=(num1);
b<=(num2);
if(add)then
c<=a+b;
end if;

if(sub)then
c<=a-b;
end if;

if(mult)then
c<=a*b;
end if;
end process;



--display the upper and lower nibbles of the operands and result on the LED digits

least_significant_digit_num1:led_decoder port map(i => num1(3 downto 0), o => LEDout); dec_in<="00";
most_significant_digit_num1:led_decoder port map(i => num1(7 downto 4), o => LEDout); dec_in<="01";


least_significant_digit_num2:led_decoder port map(i => num2(3 downto 0), o => LEDout); dec_in<="10";
most_significant_digit_num2:led_decoder port map(i => num2(7 downto 4), o => LEDout); dec_in<="11";


least_significant_digit_c:led_decoder port map(i => c(3 downto 0), o => LEDout);
most_significant_digit_c:led_decoder port map(i => c(7 downto 4), o => LEDout);

end Behavioral;