Need help on how to use functions correctly

Discussion in 'VHDL' started by Panic, Aug 25, 2003.

  1. Panic

    Panic Guest

    I am working on an implementation of the Rijndael encryption algorithm,
    and in one of my behavioral architectures, I call a function from a package
    I have written, that do a simple table lookup to transform a eight bit
    vector
    into another eight bit vector.

    My problem is that I keep getting error messeges from my compiler, that
    complaints about "Prefix name 'sub_byte' is not a 1 dimentional
    array or a function or contains a bad suffix (index/slice/selected-name)"
    when I try to call the function sub_byte (that belongs to the package
    srd_lookup_pkg)
    from a process in the behavioral architecture of my key_shedule-file.

    I have tried to supply the function with an explicit argument, like
    sub_byte(x"63"), and with a signal of the correct type (statebyte),
    but nothing seems to help. So what am I missing here?

    I use the compiler that comes with Symphony EDA Sonata 2.1 (Free Edition).

    Sincerely
    -Panic

    I include some of the contents of some of the files, so you all can get
    an impression on how my function call fits in to my design:

    ----------------------------------------------------------------------------
    ---------------
    srd_lookup_pkg.vhd
    ----------------------------------------------------------------------------
    ---------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    package srd_lookup_pkg is
    subtype statebyte is STD_LOGIC_VECTOR (7 downto 0);
    subtype halfbyte is STD_LOGIC_VECTOR (3 downto 0);
    end package srd_lookup_pkg;

    package body srd_lookup_pkg is
    function sub_byte (signal state : in statebyte ) return statebyte is
    variable sub : statebyte;
    begin
    case state is
    WHEN x"00" => sub := x"63";
    [...]
    WHEN x"FF" => sub := x"16";
    WHEN OTHERS => sub := x"00";
    end case;
    return sub;
    end sub_byte;
    end package body srd_lookup_pkg;

    ----------------------------------------------------------------------------
    ---------------


    ----------------------------------------------------------------------------
    ---------------
    key_schedule.vhd
    ----------------------------------------------------------------------------
    ---------------
    library ieee;
    use ieee.std_logic_1164.all;
    use work.types.all;
    use work.srd_lookup_pkg.all;

    entity key_schedule is
    port ( key : in std_logic_vector (127 downto 0); -- 128 bits nøkkel
    load_key : in std_logic; -- 1 = load, 0 = norm. op.
    reset : in std_logic; -- Reset
    round : in integer range 1 to 10; -- Angir runde
    round_key : out std_logic_vector (127 downto 0) ); -- =
    ExpandedKey[round]
    end entity key_schedule;

    architecture behave of key_schedule is
    signal srd_tmp : statebyte;
    begin
    load : process(load_key) is
    variable expKey : exp_key;
    variable RC : rcs;
    begin

    -- Short
    for j in 4 to 43 loop
    if j mod 4 = 0 then
    srd_tmp <= x"A2";
    expKey(j)(0) := expKey(j-4)(0) xor sub_byte(srd_tmp) xor
    RC(j/4);
    else
    -- blah blah...
    end if;
    end loop;

    end process load;
    end architecture behave;
    ----------------------------------------------------------------------------
    ---------------


    ----------------------------------------------------------------------------
    ---------------
    types.vhd
    ----------------------------------------------------------------------------
    ---------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.srd_lookup_pkg.all;

    package types is
    type rcs is array (0 to 10) of statebyte;
    type col is array (3 downto 0) of std_logic_vector (7 downto 0);
    type state is array (3 downto 0) of col;
    type exp_key is array (43 downto 0) of col;
    end package types;
     
    Panic, Aug 25, 2003
    #1
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