(newbie) processo or not process?

[Max]

I need that ch_en signal does low when reset is low; when reset is
high I need to write ch_en only when regen_en is '1' and I have
rising edge of wr.

I wrote the following codes:
----------version 1 ------------------
process (reset, regen_en, wr)
begin
if reset = '0' then
ch_en = '0';
elsif regen_en = '1' and rising_edge(wr) then
ch_en <= ctrl_data_bus(0);
end if;
end process;
--------------------------

----version 2--------------------------
ch_en <= '0' when reset = '1' else
ctrl_data_bus(0) when regen_en = '1' and rising_edge(wr);
--------------------------------------

I don't know if it make sense to use rising_edge() out of a process
block.

I think thant version 1 is correct, and I have some doubt about
version 2.
Anyway is better to use version 1 or version 2?

thanks

 

[Ralf Hildebrandt]

Hi Max!

I wrote the following codes:
----------version 1 ------------------
process (reset, regen_en, wr)
begin
if reset = '0' then
ch_en = '0';
elsif regen_en = '1' and rising_edge(wr) then
ch_en <= ctrl_data_bus(0);
end if;
end process;
--------------------------

Is the follwoing, what you are searching for?

process (reset, wr)
begin
if reset = '0' then
ch_en = '0';
elsif rising_edge(wr) then
if regen_en = '1' then
ch_en <= ctrl_data_bus(0);
end if;
end if;
end process;


This is a standart-flipflop.


Ralf

 

[Mikhail Matusov]

Your first version is almost correct, but I am not sure if your write enable
signal will be properly recognized by tools. Here is more classic flip-flop
with async reset and enable:

process (reset, wr) -- write enable shouldn't be on the sensitivity list
begin
if reset = '0' then
ch_en = '0';
elsif rising_edge(wr) then
if regen_en = '1' then
ch_en <= ctrl_data_bus(0);
end if;
end if;
end process;

rising_edge() can only be used in a process...


/Mikhail

 

[Marcus Harnisch]

rising_edge() can only be used in a process...

rising_edge() is a function defined in the package std_logic_1164. Why
would you not be able to use it outside a process? I do that on a
regularl basis.

In particular Max's second version is indeed a valid way to describe a
DFF. It is described in section "6.1.3.5. Edge-sensitive storage using
concurrent signal assignment statements" in the current 1076.6 draft
document (http://vhdl.org/siwg/66_D6X.PDF).

-- Marcus

 

[Mikhail Matusov]

rising_edge() is a function defined in the package std_logic_1164. Why

would you not be able to use it outside a process? I do that on a
regularl basis.

In particular Max's second version is indeed a valid way to describe a
DFF. It is described in section "6.1.3.5. Edge-sensitive storage using
concurrent signal assignment statements" in the current 1076.6 draft
document (http://vhdl.org/siwg/66_D6X.PDF).

This is an interesting document, however it is a draft and I am not sure how
many of the existing synthesis tools will properly recognize such a
construct...

/Mikhail

 

[Renaud Pacalet]

Well, just because it's a draft doesn't mean its entire contents is in
draft state. Unfortunately I don't have access to any released versin
of the standard. So I cannot say whether this description style was
part of earlier versions already.

As far as synthesis tools are concerned, I am quite disappointed. Not
that I ever felt the urge to use that way to describe a register, but
still. Synopsys doesn't even compile that code, claiming it contained
a syntax error :-(

Leonardo synthesizes this style very well:

-- input file:
entity DFF is
port(RESET, SET, ASYNC_LOAD: in Boolean;
A, D, CLOCK: in Bit;
Q: out Bit);
end entity DFF;

architecture ARC of DFF is
begin
COND_SIG_ASSGN: Q <= '0' when RESET else
'1' when SET else
A when ASYNC_LOAD else
D when CLOCK'EVENT and CLOCK = '1';
end architecture ARC;

-- output netlist:
library IEEE;
use IEEE.STD_LOGIC_1164.all;

package components is
component DFF
port (
Q : OUT std_logic ;
D : IN std_logic ;
CLK : IN std_logic ;
CLRN : IN std_logic := '1' ;
PRN : IN std_logic := '1') ;
end component ;
end components ;


package body components is
end components ;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DFF is
port (
RESET : IN std_logic ;
SET : IN std_logic ;
ASYNC_LOAD : IN std_logic ;
A : IN std_logic ;
D : IN std_logic ;
CLOCK : IN std_logic ;
Q : OUT std_logic) ;
end DFF ;

architecture ARC of DFF is
signal nx14, nx18: std_logic ;

begin
reg_Q : work.components.DFF port map ( Q=>Q, D=>D, CLK=>CLOCK,
CLRN=>nx18, PRN=>nx14);
nx14 <= (not SET and not A) or (not SET and not ASYNC_LOAD) or
(RESET) ;
nx18 <= (not RESET and A) or (not RESET and not ASYNC_LOAD) or
(not RESET and SET) ;
end ARC ;

Nice, isn't it?

Regards,

 

[Marcus Harnisch]

Hi Renaud,

Leonardo synthesizes this style very well:

I am not surprised. Mentor has always had better VHDL support than
Synopsys.

-- Marcus

 

[J. Bhasker]

This is an interesting document, however it is a draft and I am not sure how
many of the existing synthesis tools will properly recognize such a
construct...

/Mikhail

The draft will be an IEEE Standard soon. Couple of weeks ago, it passed an
IEEE ballot successfully. It should be a standard by the end of the year -
IEEE Std 1076.6-2003.

- J. Bhasker, Chair, IEEE VHDL Synthesis Interoperability Working Group