Newbie question. Allocators unsupported ?

[HansWernerMarschke]

I´ve tried to define a dynamic data structur in VHDL.
I´m using the Xilinx ISE Webpack 9.2.
During compilation I got the message "Allocatora unsupported".
What is the reason for this behaviour ?

library IEEE;
library STD;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;


entity enigma is
Port (input : in STD_LOGIC; output : out STD_LOGIC; mode : in
Bit);

-- The wheel type
type wheel_index is range 0 to 30;
type wheel_string is array (wheel_index'left to wheel_index'right) of
character;
type wheel_array is array (0 to 11) of wheel_string;

-- The rotor type
type rotor_type is
record
wheel_number : integer;
wheel : wheel_string;
start : character;
stepsize : integer;
position : integer;
end record;

-- The pointer to the rotor type
type rotor_pointer is access rotor_type;

-- The enigma type
type enigma_type is
record
chars : integer;
rotors : integer;
alphabet : wheel_string;
rotor : rotor_pointer;
end record;
-- This is the only global variable
-- Must be declared as "shared" to use it global
shared variable the_enigma : enigma_type;
end enigma;

Somewhere else in the programm.
This does not work.

-- Allocate memory for the rotors
the_enigma.rotor := new rotor_type;


Thank you for help

 

[HansWernerMarschke]

Thank´s for your answer Brian.
I got the error by using "create schematic symbol" although I don´t
know what this exactly means.
Till know I´ve never done hardware programming. I only know some C, C+
+, ADA, PL1 and some other languages.
So what is the difference between simulation and synthesis ?
What are you allowed to do or which programm constructs can you use
and which not ?
Are dynamic data structures the only thing which is forbidden for
synthesis ?
I would be glad to have a running simulation and get some more
experience with the Xilinx ISE tool.
You can do a syntax check in Xilinx ISE. Is there also a check if the
code is ready for synthesis ?
Which steps in the design process can you use if you are only doing a
simulation ?
What is the better tool for simulation the Xilinx ISE simulator or the
Modelsim starter edition ?
What is the difference between the free Xilinx ISE Webpack edition and
the comercial edition ?
As I was told and I understood the only difference is that you can not
programm all FPGA's with the free edition ?
Ok. I will look into the tutorials for the Xilinx ISE.