adding std_logic

[sed_y]

hi, consider the following mux code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity examp1_pg165 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           sel : in  STD_LOGIC;
           y : out  STD_LOGIC);
end examp1_pg165;

architecture Behavioral of examp1_pg165 is
  
begin
     y<= a + b when sel='1' else 
	      a+c ;
end Behavioral;

this gives an error in xilinX ISE as

 + can not have such operands in this context.

1)So, even after including numeric library, I cannot use '+' with std_logic?
2) so, do i need to convert to signed/unsigned and then add?
3) what is the safest way to use numeric libraries?

• 
  

     use IEEE.STD_LOGIC_ARITH.ALL;
     use IEEE.STD_LOGIC_SIGNED.ALL;
     use IEEE.STD_LOGIC_UNSIGNED.ALL;

or

• 
  

     use IEEE.NUMERIC_STD.ALL;
     use IEEE.STD_LOGIC_SIGNED.ALL;
     use IEEE.STD_LOGIC_UNSIGNED.ALL;

some authors say, unsigned library is not needed, others say, signed is not needed.
while some say, do not use std_logic_arith with signed/unsigned.
between numeric_std and std_logic_arith, one can make a choice based upon the operators defined. I believe, if more type conversions are needed, std_logic_arith would be better as it has more operator overloading, but it no Boolean operators?
4) The else clause covers other std_logic values. for synthesis point of view, suppose sel takes 'z', then too, y<-a+c. In real world application, would we do this, or write disconnect the mux by using something like

 y<= a + b when sel='1' else 
	      a+c  when sel ='0' else
               'z';

Thanks
sid

 

[joris]

You can sum variables declared as unsigned (or integer), but not std_logic;

You are trying to add two one-bit values and store the result in a one bit, that can't work since 1+1 = 2 = (10)binary,
requiring two bits to store the value.

If I assume you meant y declared as

  y : out std_logic_vector(1 downto 0);

Then this should work:

y<= unsigned('0' & a) + unsigned('0' & b) when sel='1' else 
	      unsigned('0' & a)+unsigned('0' & c);

Each input is concatenated with '0' and "cast" to a two-bit unsigned variable.

Oh and you are advised to replace all those signed/unsigned libraries with:

  use library ieee.Numeric_STD.all;

This one is standardized, the others are not.

 

[sed_y]

hi joris,
thanks. well, i was not worried about the carry, as I just wanted to see how the synthesizer optimizes the circuit. so, what i did was following

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity examp1_pg165_op is
    Port ( a : in  std_logic;
           b : in  std_logic;
           c : in  std_logic;
           sel : in  std_logic;
           y : out  std_logic);
end examp1_pg165_op;

architecture Behavioral of examp1_pg165_op is

signal a1,b1,c1,y1,y2:unsigned(0 downto 0) ;
signal y3:std_logic_vector(0 downto 0) ;
begin
     a1<= conv_unsigned(a,1);
	  b1<= conv_unsigned(b,1);
	  c1<= conv_unsigned(c,1);
	  y1<= b1 when sel='1' else  
	       c1 ;
	  y2<= a1+ y1;  	 
	  y3<= conv_std_logic_vector(y2,1);
	  y<=y3(0);
end Behavioral;

looks all right?
as for the library, when i create a file in VHDl in XILINX ISE, it automatically adds std_logic_arith. so, does it mean that it considers this as the standard numeric library than numeric_std?
thanks
sid

 

[joris]

I don't know, it may be the Xilinx tool recommends it.
The reason to avoid that one, is that it isn't truly standardized -- different tools may have incompatibilities.

BTW, just to state the obvious, when discarding the carry, it should just boil down to a XOR of the inputs.

 

[sed_y]

hi,
just to check what you told, when i did the following:

unsigned('0' & a) + unsigned('0' & b)

it gives error :

Expression in type conversion to unsigned has 4 possible definitions in this scope

i guess the reason is '0' cld be bit/std_logic, so it does not understand whether argumento to convert to unsigned is of what type.
so, the following works

a1 <= '0'& a;   -- a1 is std_logic vector
 a11<= unsigned(a1);  -- a11 is unsigned

 

[joris]

hmm I guess it should've been

unsigned'('0' & a)

"casting" the implicit vector to the unsigned type.
Guess that's the case I always get wrong

 

[sed_y]

hi joris,
yes, you are right. actually, i never read type qualifier before stumbling into this , which is good.
sid