adding std_logic numbers :various methods

[sed_y]

hi guys,
I have written following programs for addition. I would like to have comments on these

1) this one adds two 1 bit std_logic numbers and gives sum, carry using std_logic_arith library

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;



entity add_stdlogic_arithlib is
    Port ( a : in  std_logic;
           b : in  std_logic;
           y : out  std_logic;
           cy : out  std_logic);
end add_stdlogic_arithlib;

architecture Behavioral of add_stdlogic_arithlib is
signal a1,b1,y1:unsigned(1 downto 0) ;
signal y2:std_logic_vector(1 downto 0) ;



begin
     a1<= conv_unsigned(a,2);  
	                             
	  b1<= conv_unsigned(b,2);
	  y1<= a1 + b1 ;                           -- 2 bit unsigned add
	  y2<= conv_std_logic_vector(y1,2); -- back to std_logic
	  cy<=y2(1);
	  y<= y2(0);


end Behavioral;

Question 1: std_logic_arith has conversion between std_ulogic and unsigned, so, "b1<= conv_unsigned(b,2);" works because std_logic is subtype of std_ulogic?

2) this code does the same as above but using numeric_std library . here, the library does not specify std_ulogic to unsigned, so I first make std_logic_vector and then convert and add.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity add_stdlogic_numlib is
    Port ( a : in  std_logic;
           b : in  std_logic;
           y : out  std_logic;
           cy : out  std_logic);
end add_stdlogic_numlib;

architecture Behavioral of add_stdlogic_numlib is
signal a11,b11,y1:unsigned(1 downto 0) ;
signal a1,b1:std_logic_vector(1 downto 0) ;

begin	  
	 
     a1 <= '0'& a;   -- std_logic vector
	  a11<= unsigned(a1);  -- std_logic vector to unsigned implicit, explicit using to_unsigned not defined
	  b1<= '0'& b ;
	  b11<= unsigned(b1);  
	  y1<= a11+b11;       -- unsigned sum,2 bit
	  cy<=y1(1);           
	  y<= y1(0);

end Behavioral;

Question2) This simulates and synthesis right. is there more efficient way to do it?

3) Now, I add two std_logic_vectors using std_logic_arith library.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity add_stdlogicv_arithlib is
   generic(n:integer:= 4);
    Port ( a : in  std_logic_vector(n-1 downto 0);
           b : in  std_logic_vector(n-1 downto 0);
           y : out  std_logic_vector(n downto 0));
           
end add_stdlogicv_arithlib;

architecture Behavioral of add_stdlogicv_arithlib is

begin
    	 
		  y<= std_logic_vector(signed'(signed(sxt(a,n+1)) + signed(sxt(b,n+1))));  
  end Behavioral;

Question 3) If i do not add type qualifier and do

y<= std_logic_vector(signed(sxt(a,n+1)) + signed(sxt(b,n+1)));

Xilinx gives error

 Expression in type conversion to std_logic_vector has 2 possible definitions in this scope, for example, SIGNED and std_logic_vector

Why? after signed conversion, I am adding two signed numbers, so argument for std_logic_vector is signed, why the compiler needs type qualifier signed'?

4) now, i add std_logic vectors using numeric library.There is no sxt function in numeric library, only resize, which works on signed, so I first convert std_logic_vector to signed, then resize, add
and convert back.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_stdlogicv_numlib is
    generic(n:integer:= 4);
    Port ( a : in  std_logic_vector(n-1 downto 0);
           b : in  std_logic_vector(n-1 downto 0);
           y : out  std_logic_vector(n downto 0));
 end add_stdlogicv_numlib;

architecture Behavioral of add_stdlogicv_numlib is

signal y2:signed(n downto 0) ;
begin
       	  y2<=resize(signed(a),n+1) + resize(signed(b),n+1);
           y<= std_logic_vector(y2);   

end Behavioral;

question 4) This also simulates and synthesizes well.

However, I wanted to use something like

std_logic_vector(signed(std_logic_vector'("0")&a) + signed(std_logic_vector'("0")&b));

but, since this is signed, i should be able to use 'left attribute instead of "0". But, I am not able to do so.for example

 std_logic_vector("a'left")

gives error

The expression can not be qualified by type std_logic_vector

so, what is the right way of adding the type qualifier here?

I know this is a big query, but would appreciate any help, as it would clear lot of issues.
Thanks
sid