[novice] vector signal assignment

Joined
May 22, 2010
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Hey,

I'm a beginner trying to learn some hardware programming as a hobby ;)

Since I'm into telecommunications, I've decided to start with a simple digital modulation scheme. Now I'm designing a mapper module and hence I need to perform some vector operations. Could someone please tell me why this code is not correct? My problem is I want bits 6,4,2 and 0 of the input data (8-bit) map onto a 4-bit signal so based on it I can choose value for one of the two outputs. Bits 7,5,3,1 would decide on the other output. Why doesn't the assignment from the code work? How to do it correctly?

Code:
library ieee;
use ieee.std_logic_1164.all;

entity mapper is
	port (
		clk : in std_logic;
		data : in std_logic;
		iout : out std_logic_vector(7 downto 0);
		qout : out std_logic_vector(7 downto 0)
		);
end mapper;
architecture arch of mapper is
  signal s1: std_logic_vector(3 downto 0);
begin
  s1 <= (data(6),data(4),data(2),data(0));      --<----- THIS
  with s1 select
    iout <= "00000000" when "1000",
            "00000001" when "1001";
end arch;

Thanks in advance for any help. Cheers!

------------------------------------------------------------------- UPDATE;)

Oh my, such a fail. sorry for the spam, i have just noticed that there was
Code:
data : in std_logic;
when it should be:
Code:
data : in std_logic_vector(7 downto 0);
I apologize again;) Here's the working code for 256-QAM mapping:
Code:
library ieee;
use ieee.std_logic_1164.all;

entity mapper is
	port (
		clk : in std_logic;
		data : in std_logic_vector(7 downto 0);
		iout : out std_logic_vector(7 downto 0);
		qout : out std_logic_vector(7 downto 0)
		);
end mapper;
architecture arch of mapper is
  signal s1: std_logic_vector(3 downto 0);
  signal s2: std_logic_vector(3 downto 0);
begin
  s1 <= data(6) & data(4) & data(2) & data(0);
  s2 <= data(7) & data(5) & data(3) & data(1);
  with s1 select
    iout <= "00000001" when "1000",
            "00000011" when "1001",
            "00000101" when "1011",
            "00000111" when "1010",
            "00001001" when "1110",
            "00001011" when "1111",
            "00001101" when "1101",
            "00001111" when "1100",
            "00010001" when "0100",
            "00010011" when "0101",
            "00010101" when "0111",
            "00010111" when "0110",
            "00011001" when "0010",
            "00011011" when "0011",
            "00011101" when "0001",
            "00011111" when "0000",
            "00000000" when others;
  with s2 select
    qout <= "00000001" when "1000",
            "00000011" when "1001",
            "00000101" when "1011",
            "00000111" when "1010",
            "00001001" when "1110",
            "00001011" when "1111",
            "00001101" when "1101",
            "00001111" when "1100",
            "00010001" when "0100",
            "00010011" when "0101",
            "00010101" when "0111",
            "00010111" when "0110",
            "00011001" when "0010",
            "00011011" when "0011",
            "00011101" when "0001",
            "00011111" when "0000",
            "00000000" when others;
end arch;
 
Last edited:
Joined
May 22, 2010
Messages
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0
oh my, such a fail. sorry for the spam, i have just noticed that there was
Code:
data : in std_logic;
when it should be:
Code:
data : in std_logic_vector(7 downto 0);
I apologize again;) Here's the working code for 256-QAM mapping:
Code:
library ieee;
use ieee.std_logic_1164.all;

entity mapper is
	port (
		clk : in std_logic;
		data : in std_logic_vector(7 downto 0);
		iout : out std_logic_vector(7 downto 0);
		qout : out std_logic_vector(7 downto 0)
		);
end mapper;
architecture arch of mapper is
  signal s1: std_logic_vector(3 downto 0);
  signal s2: std_logic_vector(3 downto 0);
begin
  s1 <= data(6) & data(4) & data(2) & data(0);
  s2 <= data(7) & data(5) & data(3) & data(1);
  with s1 select
    iout <= "00000001" when "1000",
            "00000011" when "1001",
            "00000101" when "1011",
            "00000111" when "1010",
            "00001001" when "1110",
            "00001011" when "1111",
            "00001101" when "1101",
            "00001111" when "1100",
            "00010001" when "0100",
            "00010011" when "0101",
            "00010101" when "0111",
            "00010111" when "0110",
            "00011001" when "0010",
            "00011011" when "0011",
            "00011101" when "0001",
            "00011111" when "0000",
            "00000000" when others;
  with s2 select
    qout <= "00000001" when "1000",
            "00000011" when "1001",
            "00000101" when "1011",
            "00000111" when "1010",
            "00001001" when "1110",
            "00001011" when "1111",
            "00001101" when "1101",
            "00001111" when "1100",
            "00010001" when "0100",
            "00010011" when "0101",
            "00010101" when "0111",
            "00010111" when "0110",
            "00011001" when "0010",
            "00011011" when "0011",
            "00011101" when "0001",
            "00011111" when "0000",
            "00000000" when others;
end arch;
 

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