or_reduce for array of std_ulogic_vectors REVISITED

  • Thread starter Richard Nicholas
  • Start date

R

Richard Nicholas

Hi all,

I posted back in November that I needed a funtion that would take as input an array of
std_ulogic_vectors and return a std_ulogic_vector which is the OR of all of the vectors in
the array. What we came up with is:

function array_or( vectors : arr) return std_ulogic_vector is

variable result : std_ulogic_vector (vectors(0)'range);

begin
result := vectors(0);
for i in 1 to arr'length-1 loop
result := result or vectors(i);
end loop;

return result;
end array_or;

where arr is defined like:

type arr is array (0 to 99) of std_ulogic_vector(0 to 15);

So array_or works for all arrays defined as type arr but not, for example, arrays of these
types:

type arr1 is array (0 to 99) of std_ulogic_vector(0 to 3);
type arr2 is array (0 to 99) of std_ulogic_vector(0 to 63);
type arr3 is array (0 to 99) of std_ulogic_vector(0 to 31);
type arr4 is array (0 to 99) of std_ulogic_vector(0 to 87);

I'm having trouble making the function general though because I will have numerous array
types that I want to use with this one function. In my case all the arrays will all have the
same number of array elements but the std_ulogic_vectors contained in the arrays have
different lengths like the examples above.

I want to be able to run array_or on diferent array types without having a function (even
overloaded) for all the different sizes of std_ulogic_vector.

Can this be done? The funtion above is already figuring out the range of the vector but I
can't figure out how to pass some kind of generic sized array to the function. Any help
would be appreciated.

Richard Nicholas
 
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K

KJ

Can this be done? The funtion above is already figuring out the range ofthe vector but I

can't figure out how to pass some kind of generic sized array to the function. Any help

Arrays of arrays that are not constrained can be problematic at times. With VHDL-2008 you can at least define unconstrained arrays of arrays however you can't always use them the way you'd like to (like what you're trying todo). I don't think there is a way to do what you want with your function and make it generic due to this limitation.

A different approach is to make a two dimensional array:
type sulv2d is array(natural range<>, natural range<>) of std_ulogic;

Now you can write your function to work with any 2D array to implement yourfunction. The complication comes if you need to work with the std_ulogic_vectors such as my_arr(3) which is no longer a std_ulogic_vector(0 to 3). You can work around that difficulty by creating to/from conversion functions that take as input the 2D array and the index of the row/column that you want to extract or assign. The to_std_ulogic_vector function would return a real std_ulogic_vector; the from_std_ulogic_vector would assign into the 2D array the elements from the input std_ulogic_vector. Those to/from functions can be generic. The other way would be to rewrite your code to work with the 2D array rather than a array of 1D vectors.

Kevin Jennings
 
A

Andy

With VHDL-2008 you can at least define unconstrained arrays of arrays however
you can't always use them the way you'd like to (like what you're trying to
do). I don't think there is a way to do what you want with your function and
make it generic due to this limitation.

Just to be clear, 2008 std lets you define arrays (constrained or not) of unconstrained arrays. Prior versions of the standard required all elements of any array to be either scalar, constrained array or record types.

I was not aware of 2008 restrictions on arrays of unconstrained arrays thatwould prohibit their use as the OP desires. Restrictions that would prohibit what the OP wants would drasticly limit the applications of such arrays.Can you elaborate?

Another approach/work-around that the OP might want to try is to add a length argument to the function that explicitly defines the length of the result vector and correspondingly, the length of each of the elements of the vectors argument. Perhaps this would work around the limitations you mentioned?

This solution would still requre a type for vectors that is an array (constraine or not) of unconstrained arrays, and therefore 2008 compatibility with all tools involved. Note that very few (if any) tools support ALL 2008 enhancements, so each tool must be specifically checked (and tested) to confirm the desired feature is supported before the feature is adopted in a design.

Andy
 
R

Richard Nicholas

Just to be clear, 2008 std lets you define arrays (constrained or not) of unconstrained arrays.
Prior versions of the standard required all elements of any array to be either scalar,
constrained array or record types.
I was not aware of 2008 restrictions on arrays of unconstrained arrays that would prohibit
their use as the OP desires. Restrictions that would prohibit what the OP wants would
drasticly limit the applications of such arrays. Can you elaborate?

I would really be sad if VHDL does not allow you to write a function that can OR together an
array of std_logic_vectors without having to fix the size of the std_logic_vectors.
Another approach/work-around that the OP might want to try is to add a length argument
to the function that explicitly defines the length of the result vector and
correspondingly, the length of each of the elements of the vectors argument. Perhaps this
would work around the limitations you mentioned?

I am interested in this idea. I would be happy to pass the length into the function. Do you
know what syntax to make that work?

Richard Nicholas
 
R

Richard Nicholas

The complication comes if you need to work with the std_ulogic_vectors such as my_arr(3)
which is no longer a std_ulogic_vector(0 to 3).

Right. I do need to use to my_arr(3) as a std_ulogic_vector.
You can work around that difficulty by creating to/from conversion functions...

Ug. Thanks for the suggestions. I'll continue to search for a cleaner solution before doing
this.

Richard Nicholas
 
K

KJ

On Wednesday, January 8, 2014 7:02:20 PM UTC-6, KJ wrote:
I was not aware of 2008 restrictions on arrays of unconstrained arrays that
would prohibit their use as the OP desires. Restrictions that would prohibit
what the OP wants would drasticly limit the applications of such arrays. Can
you elaborate?

Actually, it might work after all. I had an error in my rewrite of the function 'array_or' that made that led me to believe the function wasn't handling the unconstrained array of an unconstrained array. Upon reviewing, that problem has been cleaned up.

The posted code below compiles and might actually perform the intended function. If not, it should provide a decent starting point.

Kevin Jennings

library ieee;
use ieee.std_logic_1164.all;

entity foo is
end foo;

architecture rtl of foo is
subtype sulv_arr is std_ulogic_vector;
type arr is array (natural range <>) of std_ulogic_vector;

function array_or( vectors : arr) return std_ulogic_vector is

variable result : std_ulogic_vector (vectors(vectors'left)'range);

begin
result := vectors(vectors'left);
for i in vectors'range loop
result := result or vectors(i);
end loop;

return result;
end array_or;
begin
end rtl;
 
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K

KJ

Ug. Thanks for the suggestions. I'll continue to search for a cleaner
solution before doing
My later post is the cleaner solution you're looking for...whether it actually works the way you intend or not is for you to discover but at least it compiles (with VHDL 2008).

Kevin Jennings
 
R

Richard Nicholas

My later post is the cleaner solution you're looking for...whether it actually works the way you intend or not is for you to discover but at least it compiles (with VHDL 2008).

Kevin Jennings

Thank you so much. I'm looking forward to checking it out!

Richard Nicholas
 
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R

Richard Nicholas

The posted code below compiles and might actually perform the intended function.
If not, it should provide a decent starting point.

Kevin, just wanted to let you know I have tried your version of the function and its working
great! Thanks so much!

Richard Nicholas
 

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