pass value from system verilog to VHDL (std_logic_vector)

[sundar]

Hi,
In my VHDL DUT I have a generic declared as std_logic_vector as below
generic_name : std_logic_vector := "0100000000";

My verification environment is in System Verilog where I need to pass
a value to this generic during mapping it in System Verilog

dut
#(
..generic_name (),
)
....
I cudnt able to pass any value from my test bench and my Questasim
6.3c simulator states
# ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
for the associated Verilog parameter.

Please let me know your thoughts.

Thanks,
Sundar
Note: I had a workaround by leaving the dut mapping as blank and
passing value during vsim like
-g/tb/dut_0/generic_name=10'b0100000000.

 

[Marcus Harnisch]

I cudnt able to pass any value from my test bench and my Questasim
6.3c simulator states
# ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
for the associated Verilog parameter.

See section "VHDL Instantiation Criteria Within Verilog" in the Questa
User Guide. std_logic_vector is not among the supported types for
generics.

Regards
Marcus

 

[sundar]

I cudnt able topassany value from my test bench and my Questasim
6.3c simulator states
# ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
for the associated Verilog parameter.

See section "VHDL Instantiation Criteria Within Verilog" in the Questa
User Guide. std_logic_vector is not among the supported types for
generics.

Regards
Marcus

--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

(seen onhttp://www.veripool.com/verilog-mode_news.html)

Hello Marcus,
I decalred parameter inteeger type and passed it to VHDL wrapper to
convert it into std_logic_vector which helped me in this regard.

Thanks,
Sundar