post-map simulation error

[=?ISO-8859-1?Q?Ciar=E1n_Hughes?=]

Hi all.

I have a vhdl module which works fine under behavioural simulation,
and even under post-translate simulation. But when I try a post-map
simulation, I get the following error:

# ** Warning: */X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.34 ns; Observed := 0.019 ns; At : 1.2 ns
# Time: 1200 ps Iteration: 2 Instance:
/testbench/uut/go_int_2_1392

The results from the simulation are also wrong (I get a lot of 'X'
values). I am using Xilinx ISE 5.2, and Modelsim XE/II starter 5.6e.

Thanks.
Ciarán Hughes

 

[Jim Lewis]

Ciarán,

# ** Warning: */X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.34 ns; Observed := 0.019 ns; At : 1.2 ns
# Time: 1200 ps Iteration: 2 Instance:
/testbench/uut/go_int_2_1392

Your error occurs at 1.2 ns. When does reset happen?
In general you will get a number of messages before reset
and for the most part, they can be ignored.
In my testbenches, I print to the transcript window
when reset starts and when it is done. This way
I know which error messages can be safely ignored.

The results from the simulation are also wrong (I get a lot of 'X'
values). I am using Xilinx ISE 5.2, and Modelsim XE/II starter 5.6e.

This is actually a good thing. Registers in general
come up 'X' anyway. If this effects your simulation,
you are probably lacking reset on some registers that
really require it. This is one thing often masked
by behavioral simulations.

If at time 1.2 ns you are actually out of reset already,
then you may have a real problem. You need to look at your
worst case timing analysis on your place and routed design.
Will the design run at speed?

If your static timing analysis shows your design should
work, you could have a simulator rounding issue.
In this case, increase the simulator resolution
(by picking fs,10 fs, 100fs, ps, ...).

Also measure your clock waveform in the simulator window
to make sure it matches exactly what you would expect
(in modelsim use two cursors and the align with edge
functionality to get an accurate measure).

If you still have problems, try adding 1 ns to the
period of your clock. If this causes the design
to work, and your worst case static timing analysis
says the design works, you need to talk to your
AE.


Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Ciar?n Hughes]

Thanks Jim.

Your comments really helped me find out that the problem was with the
test-benches I have written, and not the VHDL modules. I have taken to
using the test-bench waveforms in Xilinx ISE, and things are running
smoothly. I am only new to VHDL, and so probably don't understand the
"ins-and-outs" of test-benches.

Thanks again
Ciarán

 

[Wong]

Thanks Jim.

Your comments really helped me find out that the problem was with the
test-benches I have written, and not the VHDL modules. I have taken to
using the test-bench waveforms in Xilinx ISE, and things are running
smoothly. I am only new to VHDL, and so probably don't understand the
"ins-and-outs" of test-benches.

Thanks again
Ciarán

Hi,
But the warning already told us that you have a 'setup time
violation' on the FF (go_int_2_1392). Though you got your right
testbench, I don't know whether you will see this again. By shifting
the signal's timing in your testbench, it would help you a lot. Please
correct me if I am wrong.
Have a nice day !