D
Drew
Hi,
I designed a 3 stage pipelined floating point adder/subtractor (IEEE
754 floating point arithmetic).
I am using Xilinx ISE 9.1a environment to code and Modelsim to
simulate.
I am getting correct outputs for all the clock cycles in behavioral
simulation. However, in Post-Route simulation, I am not getting
output for the first data pair given for the arithmetic. In the next
clock cycles, output is coming correctly. When I increased the period
to 200 ns, output is coming correctly in the first clock cycle also.
But, I did not understand why it is giving correct output when the
period is increased to 200 ns from 80 ns.
In the detailed Design summary produced after the Post-Route
simulation, I saw that the minimum time period is 24 ns. But, I am
getting output for the first clock cycle only when the period is
increased to 200 ns. Please throw some light about what is happening.
Thanks and Regards,
Vamsi.
I designed a 3 stage pipelined floating point adder/subtractor (IEEE
754 floating point arithmetic).
I am using Xilinx ISE 9.1a environment to code and Modelsim to
simulate.
I am getting correct outputs for all the clock cycles in behavioral
simulation. However, in Post-Route simulation, I am not getting
output for the first data pair given for the arithmetic. In the next
clock cycles, output is coming correctly. When I increased the period
to 200 ns, output is coming correctly in the first clock cycle also.
But, I did not understand why it is giving correct output when the
period is increased to 200 ns from 80 ns.
In the detailed Design summary produced after the Post-Route
simulation, I saw that the minimum time period is 24 ns. But, I am
getting output for the first clock cycle only when the period is
increased to 200 ns. Please throw some light about what is happening.
Thanks and Regards,
Vamsi.