real time vhdl clock

[naqiboy]

Hi guys
i got some help last time and i was happy. I was wondering if soemone could help me again.

Im trying to code a real time clock.

I coded a simple 0 to 9 counter and i think this is the basis of the clock.

I have the counter running fine, but now i want it so that after it hits 0 after a full on the first cycle, another signal starts the count and goes only upto 1. Once the first cycle completes the second time, my second signal goes to 2.

The idea is to count upto 59 and then reset to 0.

Im trying to do this first and then will move on to triggering for the minutes and hours.
In the code, ive just tried for it to go upto 39 and then come back.

Ive attached my code. does it make sense? If you have alternate coding, or other ideas, please

 

[jeppe]

You will properly find some inspiration here:
http://www.jjmk.dk/MMMI/Logic_Problems/No04_StopWatch/index.htm

Your welcome
Jeppe

 

[naqiboy]

ill look over it soon. Does my code make sense ? especially the coding for the second digit.

 

[naqiboy]

i dont understand much of the code on that link :damnmate:

 

[jeppe]

Well keep trying -
Your learning by doing (I comment your code before)
Jeppe

 

[naqiboy]

thanks, but i could really use some direction :hmm2:

 

[jeppe]

OK try this

USE ieee.std_logic_unsigned.all;


ENTITY realclock IS

                 PORT (CLOCK : IN STD_LOGIC;
                       S     : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                       SS    : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
End realclock;



ARCHITECTURE mylogic OF realclock IS

signal count : std_logic_vector (25 DOWNTO 0);
signal a , b     : std_logic;
signal D , C     : std_logic_vector (3 DOWNTO 0);

BEGIN PROCESS (CLOCK, count, a,D,C)
   Variable vD,vC:  std_logic_vector (3 DOWNTO 0);
BEGIN

IF (CLOCK'EVENT AND CLOCK = '1') THEN

   count <= count + 1;

END IF;

IF count = "01011111010111100001000000" THEN
   a<='0';
END IF;

IF count = "10111110101111000010000000" THEN
   a<='1';
   count<="00000000000000000000000000";
END IF;


-- Counts 0-9 first display (Seconds)

IF (a'EVENT AND a = '1') THEN
   vD := vD + 1;
   IF vD = "1010" THEN
      vD := "0000";
      vC := vC+1;
      if vC="0110" then
         vC := "0000";  
   END IF;
END IF;


C<=vC;
D<=vD;

S(0) <= not ((not D(2) and not D(0)) or (D(2) and D(0)) or D(3) or D(1));
     S(1) <= not ((not D(0) and not D(1)) or (D(1) and D(0)) or (not D(2)));
     S(2) <= not ((not D(1)) or D(0) or D(2)) ;
     S(3) <= not ((not D(2) and not D(0)) or (D(2) and D(0) and not D(1)) or (not D(2) and D(1)) or (D(1) and not D(0)));
     S(4) <= not ((not D(2) and not D(0)) or (not D(0) and D(1)));
     S(5) <= not ((not D(1) and not D(0)) or  (D(2) and not D(0)) or D(3) or (not D(1) and D(2)));
     S(6) <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));

S(0) <= not ((not C(2) and not C(0)) or (C(2) and C(0)) or C(3) or C(1));
     S(1) <= not ((not C(0) and not C(1)) or (C(1) and C(0)) or (not C(2)));
     S(2) <= not ((not C(1)) or C(0) or C(2)) ;
     S(3) <= not ((not C(2) and not C(0)) or (C(2) and C(0) and not C(1)) or (not C(2) and C(1)) or (C(1) and not C(0)));
     S(4) <= not ((not C(2) and not C(0)) or (not C(0) and C(1)));
     S(5) <= not ((not C(1) and not C(0)) or  (C(2) and not C(0)) or C(3) or (not C(1) and C(2)));
     S(6) <= not ((not C(1) and C(2)) or C(3) or (C(1) and not C(2)) or (C(2) and not C(0)));


end PROCESS;
END mylogic;

 

[naqiboy]

thanks alot guys as usual.
Ive made some changes to the vhdl. I know have the seconds, minute and hour counts all perfect.

Im now tryingto :

- make a simple switch that if enabled will halt the second counter at its position and when released to continue from there.

- a set switch to set the mins/hrs

- a reset switch.

Id love help on any or all of the above.

I must mention i really appreciate all the time given to this..really!

my code so far

Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY realclock IS

PORT (CLOCK : IN   STD_LOGIC;
                 S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                SS : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                M : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                MB : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                H : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                HB : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
                
                  
End realclock;



ARCHITECTURE mylogic OF realclock IS
      signal count , count2 : std_logic_vector (25 DOWNTO 0);
      signal a , b : std_logic;
      signal D : std_logic_vector (3 DOWNTO 0);
      signal C : std_logic_vector (3 DOWNTO 0);
      signal MINONE : std_logic_vector (3 DOWNTO 0);
      signal HRONE : std_logic_vector (3 DOWNTO 0);
      signal MINTWO : std_logic_vector (3 DOWNTO 0);
      signal HRTWO : std_logic_vector (3 DOWNTO 0); 
      signal leds : std_logic_vector (3 DOWNTO 0);

      
BEGIN PROCESS (CLOCK, Count, a, D, C) -- All these signal must "trig" the process
BEGIN
 --clock event
   
  IF (CLOCK'EVENT AND CLOCK = '1') THEN
           count <= count + 1;
     END IF;

     IF count = "01011111010111100001000000" THEN
          a<='0';
     END IF;

     IF count = "10111110101111000010000000" THEN
          a<='1';
         count<="00000000000000000000000000";
     END IF;

-- at a=1 1st seconds starts counting to 9
      IF (a'EVENT AND a = '1') THEN
           D <= D + 1;
           IF D = "1001" THEN  -- 
               D<="0000";
-- at the end of one 0-9 cycle, the 2nd second counter starts
C <= C+1;
IF C="0101" THEN

C<="0000";



MINONE<=MINONE + 1;

IF MINONE="1001" THEN
MINONE<="0000";

MINTWO<=MINTWO + 1;


IF MINTWO="0101" THEN 
MINTWO<="0000";


HRONE<=HRONE + 1;

IF HRONE="1001" THEN
HRONE<="0000";


HRTWO<=HRTWO + 1;

IF HRTWO="0101" THEN 
HRTWO<="0000";




END IF;
END IF;




END IF;
END IF;
           END IF;
      END IF;

END IF;



--second


--IF D = "0000"






     S(0) <= not ((not D(2) and not D(0)) or (D(2) and D(0)) or D(3) or D(1));
     S(1) <= not ((not D(0) and not D(1)) or (D(1) and D(0)) or (not D(2)));
     S(2) <= not ((not D(1)) or D(0) or D(2)) ;
     S(3) <= not ((not D(2) and not D(0)) or (D(2) and D(0) and not D(1)) or (not D(2) and D(1)) or (D(1) and not D(0)));
     S(4) <= not ((not D(2) and not D(0)) or (not D(0) and D(1)));
    S(5) <= not ((not D(1) and not D(0)) or (D(2) and not D(0)) or D(3) or (not D(1) and D(2)));
    S(6) <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));

SS(0) <= not ((not C(2) and not C(0)) or (C(2) and C(0)) or C(3) or C(1));
     SS(1) <= not ((not C(0) and not C(1)) or (C(1) and C(0)) or (not C(2)));
     SS(2) <= not ((not C(1)) or C(0) or C(2)) ;
     SS(3) <= not ((not C(2) and not C(0)) or (C(2) and C(0) and not C(1)) or (not C(2) and C(1)) or (C(1) and not C(0)));
     SS(4) <= not ((not C(2) and not C(0)) or (not C(0) and C(1)));
     SS(5) <= not ((not C(1) and not C(0)) or  (C(2) and not C(0)) or C(3) or (not C(1) and C(2)));
     SS(6) <= not ((not C(1) and C(2)) or C(3) or (C(1) and not C(2)) or (C(2) and not C(0)));


M(0) <= not ((not MINONE(2) and not MINONE(0)) or (MINONE(2) and MINONE(0)) or MINONE(3) or MINONE(1));
     M(1) <= not ((not MINONE(0) and not MINONE(1)) or (MINONE(1) and MINONE(0)) or (not MINONE(2)));
     M(2) <= not ((not MINONE(1)) or MINONE(0) or MINONE(2)) ;
     M(3) <= not ((not MINONE(2) and not MINONE(0)) or (MINONE(2) and MINONE(0) and not MINONE(1)) or (not MINONE(2) and MINONE(1)) or (MINONE(1) and not MINONE(0)));
     M(4) <= not ((not MINONE(2) and not MINONE(0)) or (not MINONE(0) and MINONE(1)));
    M(5) <= not ((not MINONE(1) and not MINONE(0)) or (MINONE(2) and not MINONE(0)) or MINONE(3) or (not MINONE(1) and MINONE(2)));
    M(6) <= not ((not MINONE(1) and MINONE(2)) or MINONE(3) or (MINONE(1) and not MINONE(2)) or (MINONE(2) and not MINONE(0)));

     

     MB(0) <= not ((not MINTWO(2) and not MINTWO(0)) or (MINTWO(2) and MINTWO(0)) or MINTWO(3) or MINTWO(1));
     MB(1) <= not ((not MINTWO(0) and not MINTWO(1)) or (MINTWO(1) and MINTWO(0)) or (not MINTWO(2)));
     MB(2) <= not ((not MINTWO(1)) or MINTWO(0) or MINTWO(2)) ;
     MB(3) <= not ((not MINTWO(2) and not MINTWO(0)) or (MINTWO(2) and MINTWO(0) and not MINTWO(1)) or (not MINTWO(2) and MINTWO(1)) or (MINTWO(1) and not MINTWO(0)));
     MB(4) <= not ((not MINTWO(2) and not MINTWO(0)) or (not MINTWO(0) and MINTWO(1)));
    MB(5) <= not ((not MINTWO(1) and not MINTWO(0)) or (MINTWO(2) and not MINTWO(0)) or MINTWO(3) or (not MINTWO(1) and MINTWO(2)));
    MB(6) <= not ((not MINTWO(1) and MINTWO(2)) or MINTWO(3) or (MINTWO(1) and not MINTWO(2)) or (MINTWO(2) and not MINTWO(0)));




H(0) <= not ((not HRONE(2) and not HRONE(0)) or (HRONE(2) and HRONE(0)) or HRONE(3) or HRONE(1));
     H(1) <= not ((not HRONE(0) and not HRONE(1)) or (HRONE(1) and HRONE(0)) or (not HRONE(2)));
     H(2) <= not ((not HRONE(1)) or HRONE(0) or HRONE(2)) ;
     H(3) <= not ((not HRONE(2) and not HRONE(0)) or (HRONE(2) and HRONE(0) and not HRONE(1)) or (not HRONE(2) and HRONE(1)) or (HRONE(1) and not HRONE(0)));
     H(4) <= not ((not HRONE(2) and not HRONE(0)) or (not HRONE(0) and HRONE(1)));
    H(5) <= not ((not HRONE(1) and not HRONE(0)) or (HRONE(2) and not HRONE(0)) or HRONE(3) or (not HRONE(1) and HRONE(2)));
    H(6) <= not ((not HRONE(1) and HRONE(2)) or HRONE(3) or (HRONE(1) and not HRONE(2)) or (HRONE(2) and not HRONE(0)));





 HB(0) <= not ((not HRTWO(2) and not HRTWO(0)) or (HRTWO(2) and HRTWO(0)) or HRTWO(3) or HRTWO(1));
     HB(1) <= not ((not HRTWO(0) and not HRTWO(1)) or (HRTWO(1) and HRTWO(0)) or (not HRTWO(2)));
     HB(2) <= not ((not HRTWO(1)) or HRTWO(0) or HRTWO(2)) ;
     HB(3) <= not ((not HRTWO(2) and not HRTWO(0)) or (HRTWO(2) and HRTWO(0) and not HRTWO(1)) or (not HRTWO(2) and HRTWO(1)) or (HRTWO(1) and not HRTWO(0)));
     HB(4) <= not ((not HRTWO(2) and not HRTWO(0)) or (not HRTWO(0) and HRTWO(1)));
    HB(5) <= not ((not HRTWO(1) and not HRTWO(0)) or (HRTWO(2) and not HRTWO(0)) or HRTWO(3) or (not HRTWO(1) and HRTWO(2)));
    HB(6) <= not ((not HRTWO(1) and HRTWO(2)) or HRTWO(3) or (HRTWO(1) and not HRTWO(2)) or (HRTWO(2) and not HRTWO(0)));




END PROCESS;
END mylogic;