shift register data

[jazziebrain]

I have written code to have data shifted into a buffer but for some
reason the output is grounded. What am I doing wrong? I have supplied
my code below. Thank you for your time and attention.

save_data: process (rst,clk)
variable count,I_temp,Q_temp: std_logic_vector(7 downto 0);
variable I_buff_temp,Q_buff_temp:std_logic_vector(23 downto 0):=
(others => '0');
begin
if (rst= '1') then

I_buff<= (others=> '0'); --buffers with data
Q_buff<= (others=> '0');

I_buff_temp:= (others=> '0'); --temp buffers that hold data
Q_buff_temp:= (others=> '0'); -- until it is full

count:=x"00"; --counts number of bytes to make
-- 188 byte packet
buff_rdy<= '0';

elsif (clk='1' and clk'event) then
if (count=0) then
I_temp:=I_in;
Q_temp:=Q_in;
I_buff_temp := I_buff_temp(23 downto 8) & I_temp;-- save first
set of data
Q_buff_temp := Q_buff_temp(23 downto 8) & Q_temp;-- into buffers
count:= count+1;
I_buff<= I_buff;
Q_buff<= Q_buff;
buff_rdy<= '0';
elsif ((count< byte_cnt) and (count>0)) then
I_temp:=I_in;
Q_temp:=Q_in;
I_buff_temp := I_buff_temp(23 downto 8) & I_temp;-- save first
set of data
Q_buff_temp := Q_buff_temp(23 downto 8) & Q_temp;-- into buffers
count:= count+1;
I_buff<= I_buff;
Q_buff<= Q_buff;
buff_rdy<= '0';
elsif (count= byte_cnt) then
I_temp:=I_in;
Q_temp:=Q_in;
I_buff_temp := I_buff_temp(23 downto 8) & I_temp;-- save first
set of data
Q_buff_temp := Q_buff_temp(23 downto 8) & Q_temp;-- into buffers
buff_rdy<='1';
I_buff<= I_buff_temp;
Q_buff<= Q_buff_temp;
count:= (others =>'0');
end if;
I_buff<=I_buff;
Q_buff<=Q_buff;
end if;
end process save_data;

 

[jazziebrain]

I get these messages in the synthesis report:

INFO:Xst:2679 - Register <I_buff> in unit <iq_buffers> has a constant
value of 000000000000000000000000 during circuit operation. The
register is replaced by logic.
INFO:Xst:2679 - Register <Q_buff> in unit <iq_buffers> has a constant
value of 000000000000000000000000 during circuit operation. The
register is replaced by logic.
Entity <iq_buffers> analyzed. Unit <iq_buffers> generated.


I do not understand why if I am using both of the input signals.
Thanks again for your time and attention.

 

[Mike Treseler]

INFO:Xst:2679 - Register <I_buff> in unit <iq_buffers> has a constant
value of 000000000000000000000000 during circuit operation. The
register is replaced by logic.

I do not understand why if I am using both of the input signals.

Because the only effective assignment to I_buff is
I_buff<= (others=> '0');

The value of I_buff_temp is not used in the first two cases
and this

I_buff<= I_buff;

is a nop.

Consider tracing code on a vhdl simulator
to debug this problem.

-- Mike Treseler

 

[jazziebrain]

Because the only effective assignment to I_buff is
I_buff<= (others=> '0');

Can you elaborate on this, please? How can I make the other
assignments effective?

The value of I_buff_temp is not used in the first two cases
and this

I_buff<= I_buff;

is a nop.

Thank you for pointing this out. I have changed my code to the
following.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity iq_buffers is
generic( byte_cnt: integer:=6
);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
I_in : in STD_LOGIC_VECTOR (7 downto 0);
Q_in : in STD_LOGIC_VECTOR (7 downto 0);
buff_rdy: out STD_LOGIC;
I_buff : buffer STD_LOGIC_VECTOR (23 downto 0);
Q_buff : buffer STD_LOGIC_VECTOR (23 downto 0));
end iq_buffers;

architecture Behavioral of iq_buffers is
--counting to 188 bytes
--signal count: std_logic_vector( 7 downto 0):= x"00";
--signal I_buff_temp,Q_buff_temp:std_logic_vector(23 downto 0);

begin

save_data: process (rst,clk)
variable count: std_logic_vector(7 downto 0);
variable I_buff_temp,Q_buff_temp:std_logic_vector(23 downto 0):=
(others => '0');
begin
if (rst= '1') then

I_buff<= (others=> '0'); --buffers with data
Q_buff<= (others=> '0');

I_buff_temp:= (others=> '0'); --temp buffers that hold data
Q_buff_temp:= (others=> '0'); -- until it is full

count:=x"00"; --counts number of bytes to make

buff_rdy<= '0';

elsif (clk='1' and clk'event) then
if (count=0) then
I_buff_temp := I_buff_temp(23 downto 8) & I_in;-- save first set
of data
Q_buff_temp := Q_buff_temp(23 downto 8) & Q_in;-- into buffers
count:= count+1;
buff_rdy<= '0';
elsif ((count< byte_cnt) and (count>0)) then

I_buff_temp := I_buff_temp(23 downto 8) & I_in;-- save first set
of data
Q_buff_temp := Q_buff_temp(23 downto 8) & Q_in;-- into buffers
count:= count+1;

buff_rdy<= '0';
elsif (count= byte_cnt) then
I_buff_temp := I_buff_temp(23 downto 8) & I_in;-- save first set
of data
Q_buff_temp := Q_buff_temp(23 downto 8) & Q_in;-- into buffers
buff_rdy<='1';
I_buff<= I_buff_temp;
Q_buff<= Q_buff_temp;
count:= (others =>'0');
end if;
end if;
end process save_data;
end Behavioral;

Consider tracing code on a vhdl simulator
to debug this problem.

I have simulated the code and have found that with the changes I have
made fix the grounded outputs but the only data that gets shifted into
the output buffers is the last data that was received, hence, only the
first eight bits are shifted and replaced in the output buffers. How
can I have fill up the buffers to their capacity instead of the first
byte? Why does this happen? Sorry for my newbie questions.

Thank you again for your response.

 

[Colin Paul Gloster]

In timestamped Fri, 17 Aug 2007 22:45:24 -0000, (e-mail address removed)
posted:
|-------------------------------------------------------------------------------|
|"[..] |
| |
|[..] I have changed my code to the |
|following. |
| |
|[..] |
|use IEEE.STD_LOGIC_ARITH.ALL; |
|use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|" |
|-------------------------------------------------------------------------------|

You do not need these packages.

|-------------------------------------------------------------------------------|
|"[..] |
| elsif (clk='1' and clk'event) then |
|" |
|-------------------------------------------------------------------------------|

Please read
WWW.VHDL.org/comp.lang.vhdl/FAQ1.html#rising_edge

|-------------------------------------------------------------------------------|
|"[..] |
| I_buff_temp := I_buff_temp(23 downto 8) & I_in|
|;-- save first set |
|of data |
| Q_buff_temp := Q_buff_temp(23 downto 8) & Q_in|
|;-- into buffers |
|[..] |
| I_buff_temp := I_buff_temp(23 downto 8) & I_in|
|;-- save first set |
|of data |
| Q_buff_temp := Q_buff_temp(23 downto 8) & Q_in|
|;-- into buffers |
|[..] |
| I_buff_temp := I_buff_temp(23 downto 8) & I_in|
|;-- save first set |
|of data |
| Q_buff_temp := Q_buff_temp(23 downto 8) & Q_in|
|;-- into buffers |
| buff_rdy<='1'; |
| I_buff<= I_buff_temp; |
| Q_buff<= Q_buff_temp; |
|[..] |
| |
|[..] |
| |
|[..] the only data that gets shifted into |
|the output buffers is the last data that was received, hence, only the |
|first eight bits are shifted and replaced in the output buffers. How |
|can I have fill up the buffers to their capacity instead of the first |
|byte? Why does this happen? Sorry for my newbie questions. |
| |
|Thank you again for your response." |
|-------------------------------------------------------------------------------|

Do you have some reason to believe that your code would allow
Q_buff_temp(23 downto 8) to change?

Regards,
C. P. G.

 

[jazziebrain]

Hello,
Thank you for your response.I am sorry for my newbie questions.

I have deleted the packages you suggested:

|-------------------------------------------------------------------------------|
|"[..] |
| |
|[..] I have changed my code to the |
|following. |
| |
|[..] |
|use IEEE.STD_LOGIC_ARITH.ALL; |
|use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|" |
|-------------------------------------------------------------------------------|

You do not need these packages.

but result in these synthesis errors:

ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/
iq_buffers.vhd" Line 42. = can not have such operands in this context.
ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/
iq_buffers.vhd" Line 45. + can not have such operands in this context.
ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/
iq_buffers.vhd" Line 47. < can not have such operands in this context.
ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/
iq_buffers.vhd" Line 47. > can not have such operands in this context.
ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/
iq_buffers.vhd" Line 51. + can not have such operands in this context.
ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/
iq_buffers.vhd" Line 54. = can not have such operands in this context.

Do you have some reason to believe that your code would allow
Q_buff_temp(23 downto 8) to change?

I believed by shifting the code in I can make Q_buff_temp(23 downto 8)
change. Do you have any suggestions on how I can make this possible? A
different approach? Thank you for your patience with my slow learning.

My objective of writing this code is to continually shift data into a
buffer until the buffer is filled (I am counting the number of bytes
being saved) then put the full buffer into the output register. The
shifting of data and every operation is suppose to be done at every
clock cycle. This is what I assumed needed to be included in order to
make this possible:

|-------------------------------------------------------------------------------|
|"[..] |
| elsif (clk='1' and clk'event) then |
|" |
|-------------------------------------------------------------------------------|

Please read
WWW.VHDL.org/comp.lang.vhdl/FAQ1.html#rising_edge

Thank you for the link, I have read and believe I have used it
properly. Did I use it wrong? Are my expectations with the code
unrealistic? How can I better my code in order to continuously fill up
a buffer? Do I need a finite state machine or case statement in order
to make this work?

Thank you again for your help.

 

[jazziebrain]

Hello all,
I have changed a line of code to
I_buff_temp := I_buff_temp(23 downto 16) & I_in & "00000000";

this seems to fill first two bytes ONLY. I am confused about
continuous data. Any suggestions would be helpful thank you.

 

[Colin Paul Gloster]

|-----------------------------------------------------------------------------------|
|"[..]I am sorry for my newbie questions." |
|-----------------------------------------------------------------------------------|

Hello,

Being a beginner is not a crime.

|-----------------------------------------------------------------------------------|
|"I have deleted the packages you suggested: |
|[..] |
|but result in these synthesis errors: |
| |
|ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/ |
|iq_buffers.vhd" Line 42. = can not have such operands in this context. |
|ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/ |
|iq_buffers.vhd" Line 45. + can not have such operands in this context. |
|ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/ |
|iq_buffers.vhd" Line 47. < can not have such operands in this context. |
|ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/ |
|iq_buffers.vhd" Line 47. > can not have such operands in this context. |
|ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/ |
|iq_buffers.vhd" Line 51. + can not have such operands in this context. |
|ERROR:HDLParsers:808 - "H:/Xilinx92i/JazzieProj/testing/ |
|iq_buffers.vhd" Line 54. = can not have such operands in this context." |
|-----------------------------------------------------------------------------------|

Reasons to avoid these packages are also given as responses to
F.A.Q.s, but if it is too much effort to mend it immediately, put them
back in (temporarily).

In different posts, Jazziebrain posted:
|-----------------------------------------------------------------------------------|
|"> Do you have some reason to believe that your code would allow |
|> Q_buff_temp(23 downto 8) to change? |
|> |
|I believed by shifting the code in I [..] |
| |
|[..]" |
|-----------------------------------------------------------------------------------|
and
|-----------------------------------------------------------------------------------|
|"Hello all, |
|I have changed a line of code to |
|I_buff_temp := I_buff_temp(23 downto 16) & I_in & "00000000"; |
| |
|this seems to fill first two bytes ONLY. I am confused about |
|continuous data. Any suggestions would be helpful thank you." |
|-----------------------------------------------------------------------------------|

You did not perform any shifting. I wonder have you mixed up some
operators? VHDL shifting operators have included since VHDL93 for
example SLL and ROL. Please consult a book.

At the risk of distracting you again from your main objective, you
seemed to miss my hint that more than one if branch is identical.

However, your main objective can have a proof of concept with most of
the functionality implemented in a single statement so writing all the
lines of code you have before getting such a simple prototype working
is not helping you.

Regards,
Colin Paul Gloster

 

[Shannon]

In different posts, Jazziebrain posted:

|--------------------------------------------------------------------------­---------|
|"> Do you have some reason to believe that your code would allow |
|> Q_buff_temp(23 downto 8) to change? |
|> |
|I believed by shifting the code in I [..] |
| |
|[..]" |
|--------------------------------------------------------------------------­---------|
and
|--------------------------------------------------------------------------­---------|
|"Hello all, |
|I have changed a line of code to |
|I_buff_temp := I_buff_temp(23 downto 16) & I_in & "00000000"; |
| |
|this seems to fill first two bytes ONLY. I am confused about |
|continuous data. Any suggestions would be helpful thank you." |
|--------------------------------------------------------------------------­---------|

You did not perform any shifting. I wonder have you mixed up some
operators? VHDL shifting operators have included since VHDL93 for
example SLL and ROL. Please consult a book.

I'll give you a nudge. your I_buff_temp(23 downto 16) or (23 downto
8) isn't going to ever change the way you have written things.

You need to stare at your code and really think about it. When in
your code do you assign a new value to I_buf_temp(23 downto x)?


Hint:

What you want is something like I_buf_temp := I_buf(23 downto 8) &
I_temp;
Then some other place: I_buf <= I_buf_temp;

Do you see the difference?

 

[jazziebrain]

|--------------------------------------------------------------------------­---------|
|"> Do you have some reason to believe that your code would allow |
|> Q_buff_temp(23 downto 8) to change? |
|> |
|I believed by shifting the code in I [..] |
| |
|[..]" |
|--------------------------------------------------------------------------­---------|
and
|--------------------------------------------------------------------------­---------|
|"Hello all, |
|I have changed a line of code to |
|I_buff_temp := I_buff_temp(23 downto 16) & I_in & "00000000"; |
| |
|this seems to fill first two bytes ONLY. I am confused about |
|continuous data. Any suggestions would be helpful thank you." |
|--------------------------------------------------------------------------­---------|

You did not perform any shifting. I wonder have you mixed up some
operators? VHDL shifting operators have included since VHDL93 for
example SLL and ROL. Please consult a book.

I'll give you a nudge. your I_buff_temp(23 downto 16) or (23 downto
8) isn't going to ever change the way you have written things.

You need to stare at your code and really think about it. When in
your code do you assign a new value to I_buf_temp(23 downto x)?

Hint:

What you want is something like I_buf_temp := I_buf(23 downto 8) &
I_temp;
Then some other place: I_buf <= I_buf_temp;

Do you see the difference?

 

[Shannon]

Hint:
Shoot...just realized in my haste I made a nasty error. Sorry
everyone!

Ok...it should read (assuming we are receiving MSB first):

I_buf_temp := I_buf(15 downto 0) & I_temp;
....
I_buf <= I_buf_temp;

Now the explaination...

Imagine a row of colored balls in front of you... 24 of them. Each
group of eight a differenct color..let's say red/green/blue.

Now a new set of 8 white balls comes in.
You grab the right most set of 16 balls (i.e. '15 downto 0) and push
them to the left, knocking the left most set of 8 to the floor in the
process. Then grab the new set of 8 red ones and put them inline on
the right. Graphically and in psuedo code:

rrrrrrrr/gggggggg/bbbbbbbb =>
gggggggg/bbbbbbbb/ & wwwwwwww

I_buf_temp := I_buf(15 downto 0) & I_temp;

Now you go back through your loop but you start with the new group.

gggggggg/bbbbbbbb/wwwwwwww

I_buf <= I_buf_temp;

A new set of orange balls comes in:

gggggggg/bbbbbbbb/wwwwwwwww =>
bbbbbbbb/wwwwwwww & oooooooo

I_buf_temp := I_buf(15 downto 0) & I_temp;

See the difference? In your code you were grabbing the same set of
balls everytime:

rrrrrrrr/gggggggg/bbbbbbbb =>
rrrrrrrr/gggggggg/ & wwwwwwww
rrrrrrrr/gggggggg/wwwwwwww
rrrrrrrr/gggggggg/ & ooooooo

I hope this makes it a tiny bit clearer. I really feel bad about my
mistake probably adding to your confusion. I'm surprised no one else
chastized me.

Shannon

 

[Shannon]

Now a new set of 8 white balls comes in.

You grab the right most set of 16 balls (i.e. '15 downto 0) and push
them to the left, knocking the left most set of 8 to the floor in the
process. Then grab the new set of 8 red ones and put them inline on

that should read "...new set of 8 white ones and....

Shannon

 

[jazziebrain]

I really feel bad about my mistake probably adding to your confusion.
No worries, keeps me in suspense j/k. On the contrary, thank you
for taking the time to help me out, more confused I could not have
been.


I really like your "balls" example, I am a visual learner so it was
perfect!

For everyone else that found themselves in the rut that I was in. Here
is the code that works.
I took out the a couple unnecessary if statements so my code now looks
like this:

save_data: process (clk,I_in,Q_in)
variable count,I_temp,Q_temp: std_logic_vector(7 downto 0);
variable I_buff_temp,Q_buff_temp:std_logic_vector(23 downto
0):=(others => '0');
begin
if (rst= '1') then

I_buff<= (others=> '0'); --buffers
with data
Q_buff<= (others=> '0');

I_buff_temp:= (others=> '0'); --temp
buffers that hold data
Q_buff_temp:= (others=> '0'); -- until it
is full


count:=x"00"; --counts number
of bytes to make

buff_rdy<= '0';

elsif (clk='1' and clk'event) then
I_temp:=I_in;
Q_temp:=Q_in;
if ((count >= 0) and (count <= byte_cnt)) then

I_buff_temp := I_buff_temp(15 downto
0) & I_temp;-- save first setof data
Q_buff_temp := Q_buff_temp(15 downto
0) & Q_temp;-- into buffers
I_buff<=I_buff_temp;
Q_buff<=Q_buff_temp;
count:= count+1;
buff_rdy<= '0';
if (count= byte_cnt) then
buff_rdy<='1';
count:= (others =>'0');
end if;
elsif (count > byte_cnt) then
count:= (others =>'0');
end if;


end if;
end process save_data;

Thank you very much Shannon for shining a bright light into my dark
and confused reality.
I see, I was referencing the shifted bits wrong. To begin with, I was
confused as to how I was supposed to set up my concatenated bits,
i.e.,
I_buff_temp := I_buff_temp(15 downto 0) & I_temp;
-or-
I_buff_temp := I_buff_temp(23 downto 8) & I_temp;
-or-
I_buff_temp := I_temp& I_buff_temp(23 downto y); ...etc.

but I see now thank you Shannon and Colin for all your help. **Big
sigh

On another note, I can add a few more signals to make this into a FIFO
right?