Synthesis of following code doesnot generate any component for var3, but
will the code generate a latch or flipflop for var1 and var2 ?
...
signal s1,s2,s3,s4 : std_logic;
begin
process(clk, rst)
variable var1, var2,var3,var4 : std_logic;
begin
if rst='1' then
var1:='0' ; var2:='0';
elsif(clk'event and clk='1') then
var1:=s1;
var2:=s2;
s3<= var1 xor var2;
var3:= s3 xor s4;
s4<=var3;
end if;
end process;
Why not try it? Is this homework, interview puzzle, a
simplified version of something you're working on, or
just something you imagined in a quiet moment???
First off, the code is very flaky anyway. s3 and s4
are clearly synthesised to flipflops, but they don't
appear in the "reset" branch of the process. That
implies they must have (not rst) as a clock enable.
Most synth tools will issue a warning, or even an
error, for this style problem.
The rules for flip-flop inference are quite simple
(although it can sometimes be tricky to apply them,
if the code is complicated). If there is ANY path of
execution of the process that requires you to USE the
value of a variable BEFORE you assign to it, then
of course you're picking up the value that was given
to the variable on the previous clock cycle and so it
must be stored in a flip-flop. If, however, there
is NO path through the process that uses the variable's
value before assigning to it, then the variable simply
represents some intermediate stage in the combinational
logic driving the D inputs of your clocked process's
flipflops, and the variable itself will not infer
a storage element.
The assignments to var1 and var2 in the reset branch
of the process seem to imply a latch, but the latched
values are never used within the process and therefore
the synthesis tool should recognise that no latch is
required - or, just possibly, give you a warning
message. If you see a latch, then go out and get
a synthesis tool that works.
That's it. Easy. It's very easy to apply these
rules to your piece of code.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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