Simple 8253 (beginner)

Discussion in 'VHDL' started by aleksa, Jul 30, 2008.

  1. aleksa

    aleksa Guest

    This is what I have in mind:

    1. Counter counts to zero, issues an IRQ, and reloads.
    2. The CPU gets the IRQ and writes the new 'reload' value,
    which should remove the IRQ.

    signal counter, reload : STD_LOGIC_VECTOR (15 downto 0);

    if falling_edge(clock) then
    if counter = 0 then
    counter <= reload;
    irq <= '1';
    counter <= counter - 1;
    -- irq <= '0'; -- AUTO EOI
    end if;
    end if;

    if rising_edge(write) then
    reload <= dbus; -- reload value
    irq <= '0'; -- acknowledge IRQ, EOI
    end if;

    If I use one process, webpack is giving me an error:
    Multi-source in Unit <test> on signal <irq>; this signal is connected
    to multiple drivers

    If I use two processes: Signal irq cannot be synthesized.
    Something like, irq is bound to two clocks.

    AUTO EOI works (in simulation, dont even have the chip yet),
    but the clock can be as low as 30Hz, which is too slow.

    How should I ACK an IRQ with the CPU?
    aleksa, Jul 30, 2008
    1. Advertisements

  2. aleksa

    Tricky Guest

    You cannot drive 1 signal from multiple sources. You will have to
    create a mux process and a IRQ_select signal that connects IRQ to the
    correct signal at any given time.
    Tricky, Jul 31, 2008
    1. Advertisements

  3. aleksa

    aleksa Guest

    aleksa, Jul 31, 2008
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.