Simulation warning in Modelsim

[Naimesh Thakkar]

Hello

I am getting following warning during simulation in ModelSim


* Warning: *DFE3C RECOVERY High VIOLATION ON CLR WITH RESPECT TO CLK;


# Expected := 1 ns; Observed := 0 ns; At : 61005 ns
# Time: 61005 ns Iteration: 1

Can any one tell what is RECOVERY High VIOLATION.
Thank for any help


Naimesh

 

[Allan Herriman]

Hello

I am getting following warning during simulation in ModelSim


* Warning: *DFE3C RECOVERY High VIOLATION ON CLR WITH RESPECT TO CLK;


# Expected := 1 ns; Observed := 0 ns; At : 61005 ns
# Time: 61005 ns Iteration: 1

Can any one tell what is RECOVERY High VIOLATION.
Thank for any help

Didn't you ask this same question in comp.arch.fpga recently?


Inputs to a ff must be stable just before until just after the active
edge of the clock for reliable operation.

You seem to have a transition on the async reset input at about the
same time as the active transition on the clock.

Moral: avoid using async reset inputs on ffs as a means of
implementing logic functions.

Regards,
Allan

 

[Martin Bishop]

Naimesh

You haven't specified your device or the details of your toolset (i.e.
simulation libraries).

However, I presume you're running a VITAL simulation.

If the documentation doesn't help, you should read the source for the VITAL
model to identify which timing check has been violated; enjoy the spaghetti
code.

A work-around approach to this issue is to control the relationship between
Reset and the active clock edge in the Testbench; e.g.
wait until falling_edge(Clk); -- sync to inactive clock edge
Reset_n <= '0'; -- release reset
Note that at 12" to the foot, you will get recovery time violations ...

If you read the following threads, in comp.lang.vhdl, you will be
enlightened as to how to fix this issue at 12" to the foot:
-11 1552 Sep04 : Stefan Oedenkoven : Statemachine working on Xilinx ...
-29 14:16 Jul 04 : The Weiss Famly : Asynchronous signal problem

The second thread concrens the general problem of asynchronous signals, of
which asynchronous resets are a subset. If metastability and synchronisers
are news to you read up on them in the VHDL FAQ and using Google, and apply
the techniques to your designs.

HTH

Martin