Hi,
I have a state machine. In a particular state the system goes to power save mode where the clock will be stopped.
At this state the state machine looking for an external signal, when It gets the statemachine sends a signal to analog block to start the clock and when it get the clock it will continue the state machine.
How this particular state can be done?
the design will be done in Verilog
Any input are highly appreciated.
I have a state machine. In a particular state the system goes to power save mode where the clock will be stopped.
At this state the state machine looking for an external signal, when It gets the statemachine sends a signal to analog block to start the clock and when it get the clock it will continue the state machine.
How this particular state can be done?
the design will be done in Verilog
Any input are highly appreciated.