VHDL and .txt

Discussion in 'VHDL' started by strykaar, Sep 14, 2006.

  1. strykaar

    strykaar

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    Hi All

    I am trying to read and write(after modifying) some data from/to a text file and I am using the below program. I am using Xilinx ISE 8.2i, when I synthesize it, i am getting the error that the "File <infile> does not exist.", Please help me as I am unable to remove the error.


    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_textio.all;
    USE std.TEXTIO.ALL;
    ENTITY square IS
    PORT( go : IN std_logic);
    END square;
    ARCHITECTURE simple OF square IS
    BEGIN
    PROCESS(go)
    FILE infile : TEXT IS IN "C:\infile.txt";
    FILE outfile : TEXT IS OUT "C:\outfile.txt";
    VARIABLE out_line, my_line : LINE;
    VARIABLE int_val : INTEGER;
    BEGIN
    WHILE NOT( ENDFILE(infile)) LOOP
    -- read a line from the input file
    READLINE( infile, my_line);
    -- read a value from the line
    READ( my_line, int_val);
    -- square the value
    int_val := int_val **2;
    -- write the squared value to the line
    WRITE( out_line, int_val);
    -- write the line to the output file
    WRITELINE( outfile, out_line);
    END LOOP;
    END PROCESS;
    END simple;

    Thanks

    Sandeep
     
    strykaar, Sep 14, 2006
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  2. strykaar

    Adrian Jongenelen

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    It is my understanding that text io can't actually be synthesized.

    If this is for a testbench it would (should) work fine, but with Xilinx ISE8.2 the source should not be under the 'Synthesis/Implementation' tab.
     
    Adrian Jongenelen, Sep 27, 2006
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