VHDL: AXI-stream FIFO

[HMSStanley]

Hi there,
I am a newbies in VHDL, and currently still learning, could anyone kindly advise how i can start coding VHDL on Vivado a FIFO using AXI stream that receive a data-in with 64 Bytes containing 0xEEFFAAFFAAFFAAFFAAFFAA......
Do i need a Finite state machine to start with ? Pls advise, thanks in advance..
Stanley

 

[Kuncode]

Yes, you can start with a finite state machine (FSM) to implement your FIFO using AXI stream in Vivado. Here is a basic outline of steps you can follow:

1. Create a project in Vivado and add a new VHDL source file.
2. Write a VHDL entity to define the inputs and outputs of your FIFO.
3. Write an architecture for the FIFO which includes the FSM and memory for storing data.
4. In the FSM, implement the state transitions based on the input data and the current state.
5. Implement the write and read operations to the memory.
6. Implement the AXI stream interface for the FIFO, including the data-in and data-out signals.
7. Simulate the design to verify its functionality.
8. Synthesize the design and generate bitstream for implementation on a FPGA.

This is a high-level outline and you will need to refer to the Vivado documentation and VHDL language references for more details on the implementation.

 

[HMSStanley]

thanks for the reply, could you advise any website/ tutorial that implement this? or could you kindly advise how to create .xpr files that create a FSM and fifo to the dual port ram?

Yes, you can start with a finite state machine (FSM) to implement your FIFO using AXI stream in Vivado. Here is a basic outline of steps you can follow:

1. Create a project in Vivado and add a new VHDL source file.
2. Write a VHDL entity to define the inputs and outputs of your FIFO.
3. Write an architecture for the FIFO which includes the FSM and memory for storing data.
4. In the FSM, implement the state transitions based on the input data and the current state.
5. Implement the write and read operations to the memory.
6. Implement the AXI stream interface for the FIFO, including the data-in and data-out signals.
7. Simulate the design to verify its functionality.
8. Synthesize the design and generate bitstream for implementation on a FPGA.

This is a high-level outline and you will need to refer to the Vivado documentation and VHDL language references for more details on the implementation.