VHDL code in Latex

Discussion in 'VHDL' started by Enes Erdin, Aug 1, 2009.

  1. Enes Erdin

    Enes Erdin Guest


    Recently I am trying to put some VHDL codes in a report written by
    Latex. Although I have found some information about how to do it I
    could not apply it in the report. My aim is not to use the Verbatim
    style, I want to write some piece of code and add caption to it. For
    that purpose listing package seems to be the most suitable package for
    doing it but it does not truly represent the code. I wonder how you
    guys are doing such things. The page which I mostly used about this
    was http://en.wikibooks.org/wiki/LaTeX/Packages/Listings and if you
    are interested, I can also send my "wrong compiling" piece of writing.

    Thanks in advance,

    Enes Erdin, Aug 1, 2009
    1. Advertisements

  2. Enes Erdin

    sleeman Guest

    I've always used verbatim mode... so thanks for the pointer to
    listings! If this is a smallish piece of custom formatting I've
    always been afraid to learn how to get Latex to do it. Instead, I just
    postprocessed externally to eps (for example, highlighting in emacs
    and using postscript-print-buffer), then pulled the eps into the LaTex
    doc. Obviously, that won't work if you have a multi-page listing,

    What do you mean by "does not truly represent the code"? That the
    highlighting isn't in the style that you want? Or that it's grossly
    corrupted? You might also have more luck asking in a LaTex group than
    a VHDL group.

    - Kenn
    sleeman, Aug 1, 2009
    1. Advertisements

  3. Enes Erdin

    Enes Erdin Guest

    Thank you for the post,

    This is a good idea. But what about the captions, do they appear as a
    "figure" caption?
    The most annoying thing is, for example, I write

    a <= b;
    a := b;

    in the output it appears for both of them as

    a = b

    highlighting is a luxury for me now :)


    Enes Erdin, Aug 1, 2009
  4. If if the exact rendering is important,
    crop and save a screenshot as mycode.png,
    then include include it something like:


    -- Mike Treseler
    Mike Treseler, Aug 1, 2009
  5. I usually use the listings package for this purpose:


    architecture rtl of whatever is
    -- etc...


    -- etc...

    end rtl;

    What I like is the ability to grab a section from a file:

    \caption{\label{fig:fftentity}Sample FFT Entity }

    This way you can keep your code valid and in sync with the document.

    However, you have to keep track of the line numbers. In the past I've
    added some comments in the file and used grep and friends to extract
    this information, but it was not very elegant. It should be possible
    to do it in a more elegant way from latex itself.

    Then there's the lgrind package, but I don't know if there is a
    lgrindef file for VHDL. I've used it with other languages, even though
    it's quite some time ago.

    Petter Gustad, Aug 3, 2009
  6. You mean like the method described in section 5.7 of the listings
    documentation? It needs some work, but it is a proof of concept. To
    bad that Brooks doesn't seem to be working on this any more. I sent
    him a patch two years ago (SystemVerilog and Verilog 2005 support)
    that hasn't been included, yet.

    Marcus Harnisch, Aug 3, 2009
  7. I was not aware of this feature. Either it's a later addition, or I've
    completely missed it when I first looked at the listings package long
    time ago. Thank you for making me aware of it.

    Petter Gustad, Aug 3, 2009
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.