VHDL Matrix Not getting synthesized

[syedshafi]

Hi Friends ...I am working on the design of Memory Module which haz 8 different banks ..each having 8 Different ROws and 4 Different Coloumns and each each location holding an 4 Bit of Data...

I've declared the following syntax..I'm able simaulte and verify my code functionality ...but thye follwoing declaration iz not getting synthesized...Can I hav any alternative declarations for this instead..???

I am using Xilinx 9.2i ISE Tool.....!!


type ddrram is array (0 to 7,0 to 15,0 to 3) of std_logic_vector(3 Downto 0);

I get the follwoing Synthesis errors for the syntax which i declared abaove

Xst:783 - "F:/DDR_Wrk/ddr_Memory_Design.vhd" line 33: Matrix not supported yet.

Xst:2683 - Unexpected error found while building hierarchy.



Kindly suggest me some alternative declaration syntax which may synthsize for my Module

 

[joris]

Something like this might work:

type vec2d is array(0 to 3) or std_logic_vector(3 Downto 0);
type vec3d is array(0 to 15) of vec2d;
type ddrram is array(0 to 7) of vec3d;

-- with these, instead of mem(7,15,3) you have to use mem(7)(15)(3)