VHDL sequence of a machine


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A 5-bit signed number (two complement) is read into a machine on the push and release of an active low ley. negative values are converted into positive magnitude form and even valued number are ignored. When 8 odd valued numbers have been entered, the machine displays the average value of the set along with a ready indicator. The machine then halts and repeats the process on activation of an asynchronous master reset of active low.

I'm looking to get a step by step guide in how to attempt this question, i'm not asking anyone to write my homework for me, i'm just trying to get some help on how you would go about solving this
 
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