VHDL to CMOS

[o pere o]

In the last months we have been designing an RF CMOS chip. The next step
will be to integrate some functionality that now is run in an FPGA into
the same chip.

I guess there has to be a more or less straightforward way to translate
a VHDL description into a layout, but don't know which software package
we should be looking at. How straightforward is this? How good is the
final result? Which tools are required? Is some manual place&route of
the final logic cells (which are black boxes in our technology) still
required?

Thanks for any input!

Pere

 

[rickman]

In the last months we have been designing an RF CMOS chip. The next step
will be to integrate some functionality that now is run in an FPGA into
the same chip.

I guess there has to be a more or less straightforward way to translate
a VHDL description into a layout, but don't know which software package
we should be looking at. How straightforward is this? How good is the
final result? Which tools are required? Is some manual place&route of
the final logic cells (which are black boxes in our technology) still
required?

Thanks for any input!

Pere

Chip design is not my forte, but my understanding is that digital logic
and RF put different requirements on the process and are not often
combined on a single chip. There is typically a compelling need when
this is done, like sales of millions of chips.

Are you designing a chip with a vendor in mind? They typically can
point you to tools and provide you with libraries.

 

[react66]

In the last months we have been designing an RF CMOS chip. The next step

will be to integrate some functionality that now is run in an FPGA into

the same chip.



I guess there has to be a more or less straightforward way to translate

a VHDL description into a layout, but don't know which software package

we should be looking at. How straightforward is this? How good is the

final result? Which tools are required? Is some manual place&route of

the final logic cells (which are black boxes in our technology) still

required?



Thanks for any input!



Pere

Don't get taken for a ride buying tools. Best bet is to see if you can pay the chip vendor to layout a block for you. If you are using a larger technology for 3.3v CMOS, like .35 u, it is not too hard to synthesize a block using some legacy tool like LEONARDO, then get the vendor to do clock insertion, layout and extraction plus a static timing run, find/fix antenna problems and give you back the block for the top level layout.

You don't want to buy all the tools just to do this. The vendor might charge you $5K if you give him the Verilog netlist and some idea of the block shape.

Synthesis and simulation should be done before this handoff, and clock gating should be done if you care about power (who doesn't). It is best to keepthe synthesis under your control. Only if you are using a deep submicron process you should probably get the vendor to do this part too.

Check http://opencircuitdesign.com, I think Tim has an open synthesis tool but it might need Verilog input.

 

[o pere o]

Chip design is not my forte, but my understanding is that digital logic
and RF put different requirements on the process and are not often
combined on a single chip. There is typically a compelling need when
this is done, like sales of millions of chips.

Are you designing a chip with a vendor in mind? They typically can
point you to tools and provide you with libraries.

We are targeting UMCs mixed-mode 180nm process. This should be a process
able to put RF and digital stuff on the same chip. And yes, we get some
libraries for digital parts, just black boxes that you may layout as you
like. If you do this by hand, from RTL description for instance, this
can be cumbersome if you have more than a few dozens of boxes...

Pere

 

[o pere o]

Don't get taken for a ride buying tools. Best bet is to see if you
can pay the chip vendor to layout a block for you. If you are using a
larger technology for 3.3v CMOS, like .35 u, it is not too hard to
synthesize a block using some legacy tool like LEONARDO, then get the
vendor to do clock insertion, layout and extraction plus a static
timing run, find/fix antenna problems and give you back the block for
the top level layout.

You don't want to buy all the tools just to do this. The vendor might
charge you $5K if you give him the Verilog netlist and some idea of
the block shape.

Synthesis and simulation should be done before this handoff, and
clock gating should be done if you care about power (who doesn't). It
is best to keep the synthesis under your control. Only if you are
using a deep submicron process you should probably get the vendor to
do this part too.

Check http://opencircuitdesign.com, I think Tim has an open synthesis
tool but it might need Verilog input.

As this is for a non-profit research project, we may have the chip done
and get access to some of the tools at a (hopefully) reasonable cost. I
will have a look at the synthesis tool you mentioned -I wasn't aware of
it. Thanks!

Pere

 

[Theo Markettos]

As this is for a non-profit research project, we may have the chip done
and get access to some of the tools at a (hopefully) reasonable cost. I
will have a look at the synthesis tool you mentioned -I wasn't aware of
it. Thanks!

Are you in academia? There may be a way to get cheap access to the tools
through a national academic programme, for example Europractice in Europe:
http://www.europractice.stfc.ac.uk/welcome.html

But be aware that it may take a long time to become familiar with the tools
- if you're only going to do this once, probably worth contracting it out.

Theo

 

[o pere o]

Are you in academia? There may be a way to get cheap access to the tools
through a national academic programme, for example Europractice in Europe:
http://www.europractice.stfc.ac.uk/welcome.html

But be aware that it may take a long time to become familiar with the tools
- if you're only going to do this once, probably worth contracting it out.

Theo

Yes, we are already members of Europractice. This was the only way to go
in our previous design. And the tools we have been using were certainly
a PITA. Now that the pain is slowly receding, I was wondering which tool
would help us going on with the digital part

Pere

 

[Theo Markettos]

Yes, we are already members of Europractice. This was the only way to go
in our previous design. And the tools we have been using were certainly
a PITA. Now that the pain is slowly receding, I was wondering which tool
would help us going on with the digital part

FWIW I've used Synopsys tools, where Design Compiler is the bit that
synthesises verilog (and presumably VHDL too) into standard cells.

Theo