vhdl -> xml parser

Discussion in 'VHDL' started by =?ISO-8859-1?Q?Sch=FCle_Daniel?=, Jul 14, 2006.

  1. Hello,

    I am writing in Python small VHDL package parser
    I wonder whether there is a free VHDL -> XML parser

    so I could extract the information using one of available XML parsers

    it could be a binary or source code(language doesn't matter)

    Regards, Daniel
    =?ISO-8859-1?Q?Sch=FCle_Daniel?=, Jul 14, 2006
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  2. A VHDL source file is not valid XML so
    maybe you mean a text to XML converter.

    I don't understand how this
    would help with parsing a VHDL package.

    -- Mike Treseler
    Mike Treseler, Jul 14, 2006
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  3. =?ISO-8859-1?Q?Sch=FCle_Daniel?=

    Amal Guest

    Any language including HDLs can be parsed to a Abstract Syntax Tree or
    a Control/Data Flow graph and this intermediate format can be saved in
    say XML. And other tools (like simulators, synthesis, formal, ...) can
    use this XML to do some kind of processing or manipulate the tree and
    display it....

    EdaXML or other standards are coming that use XML for this. You can
    find some information on:
    More examples here:

    I can imagine big EDA venors already use some sort of XML
    representation. Synopsys's CoreTools (CoreAssembler, CoreCunsultant),
    and Mentor's Platform express use SPIRIT
    (http://www.spiritconsortium.com) for IP integration using XML.

    I guess a starting point is to do the parser and then define the XML
    representation and dump the parse tree or Control/Data Flow graph in
    -- Amal
    Amal, Jul 14, 2006
  4. =?ISO-8859-1?Q?Sch=FCle_Daniel?=

    Ira Baxter Guest

    Our DMS Software Reengineering Toolkit parses Verilog and VHDL
    in several dialects and can export XML. We don't often recommend
    this option because the XML is usually enormous. YMMV.

    Ira Baxter, Jul 15, 2006
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