want VHDL code for this circuit-ergent!

Discussion in 'VHDL' started by ruwani, Feb 28, 2008.

  1. ruwani

    ruwani

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    I attached my diagram as digram1.zip. here A,B and CLOCK are the input ports.

    input bits are coming from A and B and they produce 4 intermediate outputs from given 4 gates.Acording to value that coming from 2 bit counter ( c0,c1),selected gate value produce as F.the main purpose of this circuit is to behave like and,or,xor,nxor gate at a given time.

    (this circuit is based on above idea.I thought the circuit like this.if u feel any circuit or any wrong in a above circuit, please send me correct one)

    thank u!
     

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    ruwani, Feb 28, 2008
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  2. ruwani

    gzidude

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    lame

    if you want me to do your homework for you, I take cash, money order, or bank certified check

    now go away
     
    gzidude, Feb 29, 2008
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