What is the difference between 'std_logic_vecotor' and 'signed'


Z

Zhi

eg:
a : std_logic_vector(3 downto 0) :=(others=>'0');
if a <= "0111" then
addrb <=a;
a :=a+"0001";
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);
else
report "error";
end if;
I found when a ="1000", "1001","1010"... It never report "error"
I guess does it take the first left bit as 'sign'. If it is so, what
the difference between std_logic_vector and signed. And if I only want
to write 8 value to to_text. How to give the restriction.

Thanks.
 
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M

Mike Treseler

Zhi said:
What is the difference between 'std_logic_vecotor' and 'signed'


They are different types.
Declare signed or unsigned for calculations.
Use
myport <= std_logic_vector(my_signed)to wire to top level ports.

--Mike Treseler
 
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R

Ralf Hildebrandt

Mike said:
They are different types.
Declare signed or unsigned for calculations.

Let me add: IEEE.std_logic_1164 delcares

TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

while IEEE.Numeric_std declares

type UNSIGNED is array ( NATURAL range <> ) of STD_LOGIC;
type SIGNED is array ( NATURAL range <> ) of STD_LOGIC;

Therefore I would say in clumsy way: (Un)signed is the same as
std_logic_vector. But for (un)signed arithemtic operations are defined.


Ralf
 

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