What is the difference between 'std_logic_vecotor' and 'signed'

Discussion in 'VHDL' started by Zhi, May 7, 2007.

  1. Zhi

    Zhi Guest

    eg:
    a : std_logic_vector(3 downto 0) :=(others=>'0');
    if a <= "0111" then
    addrb <=a;
    a :=a+"0001";
    WRITE (buf_in,doutb);
    WRITELINE(to_text,buf_in);
    else
    report "error";
    end if;
    I found when a ="1000", "1001","1010"... It never report "error"
    I guess does it take the first left bit as 'sign'. If it is so, what
    the difference between std_logic_vector and signed. And if I only want
    to write 8 value to to_text. How to give the restriction.

    Thanks.
     
    Zhi, May 7, 2007
    #1
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  2. They are different types.
    Declare signed or unsigned for calculations.
    Use
    myport <= std_logic_vector(my_signed)to wire to top level ports.

    --Mike Treseler
     
    Mike Treseler, May 7, 2007
    #2
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  3. Let me add: IEEE.std_logic_1164 delcares

    TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

    while IEEE.Numeric_std declares

    type UNSIGNED is array ( NATURAL range <> ) of STD_LOGIC;
    type SIGNED is array ( NATURAL range <> ) of STD_LOGIC;

    Therefore I would say in clumsy way: (Un)signed is the same as
    std_logic_vector. But for (un)signed arithemtic operations are defined.


    Ralf
     
    Ralf Hildebrandt, May 8, 2007
    #3
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