Where to find std_arith?

[Hans K Eide]

I am a novice with VHDL and trying to teach myself the language.

I use to write my design in modelsim, and my compilation in quartus. But
on the design I am working with now (making a FIFI) it seems I must use
the commando use work.std_arith.all to overload the + operand.

So, where can I fond the std_arith package, and how do I map it into my
work library?

Thanks
Hans Kristian Eide

 

[Alex]

$MODELSIM_DIRECTORY\ieee\

p.s. what is FIFI?

 

[hdlcohen]

The std_arith package was replaced by the IEEE numeric_std, which is
available in the Modelsim distribution disk under vhdl_scr/ieee. I
suggest taht you transition to that package if possible.
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[Ajeetha]

Read FAQ @ http://www.vhdl.org/comp.lang.vhdl Part 1. As others noted,
you need only numeric_std pkg.

HTH
Ajeetha
www.noveldv.com

 

[jens]

p.s. what is FIFI?

FIFI = First In First In, a variant of a FINO (First In Never Out).
One of the most popular chips to accomplish that function is the
Signetics 25120, see the datasheet here:
http://www.ganssle.com/misc/wom1.jpg
http://www.ganssle.com/misc/wom2.jpg

 

[Nicolas Matringe]

jens a écrit:

FIFI = First In First In, a variant of a FINO (First In Never Out).
One of the most popular chips to accomplish that function is the
Signetics 25120, see the datasheet here:
http://www.ganssle.com/misc/wom1.jpg
http://www.ganssle.com/misc/wom2.jpg

Great!!!
Has this been actually published by Signetics?
Thanks for the good laugh anyway )

Nicolas

 

[james]

+<> p.s. what is FIFI?
+<
+<FIFI = First In First In, a variant of a FINO (First In Never Out).
+<One of the most popular chips to accomplish that function is the
+<Signetics 25120, see the datasheet here:
+<http://www.ganssle.com/misc/wom1.jpg
+<http://www.ganssle.com/misc/wom2.jpg

*****

Which is a variant of FISH - First In Still Here.

james

 

[Okashii]

Should numeric_std pkg also replace std_logic_signed and std_unsigned for
rtl synthesis? That is, does it mean it is not recommended to do arithmetic
in std_logic, but should be converted to signed or unsigned and do the
arithmetic using numeric_std?

 

[Andy Peters]

Should numeric_std pkg also replace std_logic_signed and std_unsigned for
rtl synthesis? That is, does it mean it is not recommended to do arithmetic
in std_logic, but should be converted to signed or unsigned and do the
arithmetic using numeric_std?

Yes, absolutely.

-a

 

[Jim Lewis]

Hans,
Read the paper, "VHDL Math Tricks of the Trade" that is available
at: http://www.synthworks.com/papers/index.htm

Cheers,
Jim
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