Configuration for mixed mode vhdl / Verilog

Discussion in 'VHDL' started by Rakesh YC, Jul 9, 2004.

  1. Rakesh YC

    Rakesh YC Guest

    Hi All
    My problem is I'd like to choose VHDL entity instantiated in verilog module
    via a VHDL configuration

    To summerize: I have a hierarcy "top:vhdl - verilog - verilog - vhdl:bottom"
    structure. How to write a vhdl configuration to select the file for the bottom
    instantiation?

    If such vhdl configuration type is not possible, any suggestions to solve
    this?

    Rakesh YC
     
    Rakesh YC, Jul 9, 2004
    #1
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  2. Hi Rakesh,

    See thread 'mixed Verilog/VHDL design' from botao.
    You can find some possible solutions.

    JaI

    Rakesh YC wrote:

    >Hi All
    >My problem is I'd like to choose VHDL entity instantiated in verilog module
    >via a VHDL configuration
    >
    > To summerize: I have a hierarcy "top:vhdl - verilog - verilog - vhdl:bottom"
    > structure. How to write a vhdl configuration to select the file for the bottom
    > instantiation?
    >
    >If such vhdl configuration type is not possible, any suggestions to solve
    >this?
    >
    >Rakesh YC
    >
    >
     
    Just an Illusion, Jul 9, 2004
    #2
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  3. Rakesh YC

    smoses

    Joined:
    Sep 27, 2006
    Messages:
    1
    Hi,

    I have a similar case. The only difference is my hierarchy is "top:verilog - verilog - verilog - vhdl:bottom". I can't find a way of doing this. Did you ?

    Thanks,
    smoses



     
    smoses, Sep 27, 2006
    #3
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