Data conversion: complex, real, std_logic_vector...

Discussion in 'VHDL' started by eneko, Oct 19, 2004.

  1. eneko

    eneko Guest

    Hello, I´m new in this forum and first of all hello and thanks other
    members.
    I have to implement a VHDL program which uses complex numbers and I use
    math_complex library which have a function called cmplx whitch can convert
    a real number in a complex one.
    The problem is that I need to use an std_logic_vector input, and I can´t
    convert this input in real.
    Can anyone help me?

    Thanks for all!
     
    eneko, Oct 19, 2004
    #1
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  2. You can cast integer to real something like:
    real_v := real(to_integer(unsigned(std_c)));
    See the details below.

    -- Mike Treseler

    --__________________________________
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;

    entity std2real is
    end std2real;

    architecture sim of std2real is begin
    -- Tue Oct 19 10:11:39 2004 Mike Treseler

    what : process is
    constant std_c : std_logic_vector := x"81";
    variable real_v : real;
    begin
    real_v := real(to_integer(unsigned(std_c)));
    assert real_v = real(16#81#)
    report "conversion error";
    wait;
    end process what;
    end sim;
     
    mike_treseler, Oct 19, 2004
    #2
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  3. eneko

    eneko Guest

    Thanks a lot mike, I`m very pleased.
     
    eneko, Oct 20, 2004
    #3
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