Wait statement in a Process

Discussion in 'VHDL' started by leeaby@gmail.com, Feb 18, 2007.

  1. Guest

    Hi,

    How many wait statements can we use in a process statement?
    I us Quartus II web edition for compilation. On compiling my code it
    says, we cant use multiple wait statements in the same process.
    However many books give examples of processes with multiple wait
    statements.

    I need to design a sample data transfer interface. For this i need to
    find the clock events.
    However i cannot use

    * if clk'EVENT and clk = '1' then *

    construct. What exactly i need is to wait till i get the next clock
    edge. Hope you understood the question. Any solution to it, in logic
    or code will be a great help for proceeding my project.

    Thanking You all in advance.
    Lee
     
    , Feb 18, 2007
    #1
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  2. HT-Lab Guest

    <> wrote in message
    news:...
    > Hi,
    >
    > How many wait statements can we use in a process statement?


    This depends on your synthesis tool, most high-end tools like
    Precision/Synplify can handle multiple "wait until" statements in a process
    provided they use the same clock signal.

    > I us Quartus II web edition for compilation. On compiling my code it
    > says, we cant use multiple wait statements in the same process.
    > However many books give examples of processes with multiple wait
    > statements.
    >
    > I need to design a sample data transfer interface. For this i need to
    > find the clock events.
    > However i cannot use
    >
    > * if clk'EVENT and clk = '1' then *
    >
    > construct. What exactly i need is to wait till i get the next clock
    > edge. Hope you understood the question. Any solution to it, in logic
    > or code will be a great help for proceeding my project.


    Google VHDL Finite State Machines (1,2,3 process statemachines, mealy versus
    moore etc).

    Hans
    www.ht-lab.com



    >
    > Thanking You all in advance.
    > Lee
    >
     
    HT-Lab, Feb 18, 2007
    #2
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  3. backhus Guest

    schrieb:
    > Hi,
    >
    > How many wait statements can we use in a process statement?
    > I us Quartus II web edition for compilation. On compiling my code it
    > says, we cant use multiple wait statements in the same process.
    > However many books give examples of processes with multiple wait
    > statements.
    >
    > I need to design a sample data transfer interface. For this i need to
    > find the clock events.
    > However i cannot use
    >
    > * if clk'EVENT and clk = '1' then *
    >
    > construct. What exactly i need is to wait till i get the next clock
    > edge. Hope you understood the question. Any solution to it, in logic
    > or code will be a great help for proceeding my project.
    >
    > Thanking You all in advance.
    > Lee
    >

    Hi Lee,
    as Hans mentioned, there's only one Clock signal per Process allowed.
    But when you write "...to wait till i get the next clock
    edge." do you mean any clock edge?

    For simulation you can do that easily with:

    if clk'EVENT then

    but for synthesis you need a target that supports dual edge FFs. I doubt
    that these are in your desired FPGA.
    AFAIK, the only devices that have Dual Edge FFs are some XILINX CPLDs.

    There are lots of postings about this topic in comp.lang.vhdl and
    comp.arch.fpga.

    have a nice synthesis
    Eilert
     
    backhus, Feb 19, 2007
    #3
  4. R Quijano Guest

    I have the code for a dual edge D flipflop and it seems to work fine
    in the ISE synthesis tool

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity LatchDD is
    Port (D,CLK,R : in STD_LOGIC;
    Q,QN : out STD_LOGIC);
    end LatchDD;

    architecture Behavioral of LatchDD is
    signal Q1,Q2 : std_logic;
    begin
    -- Positive Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q2<='0';
    elsif(clk'event and clk='1') then Q2<=D;
    else null; end if;
    end process;
    -- Negative Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q1<='0';
    elsif(clk'event and clk='0') then Q1<=D;
    else null; end if;
    end process;

    Q <= (Q1 or Q2);
    QN <= not(Q1 or Q2);

    end Behavioral;

    ------------------------------------

    Or you can use this that only check the edges of the clk

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity LatchDD is
    Port (D,CLK,R : in STD_LOGIC;
    Q,QN : out STD_LOGIC);
    end LatchDD;

    architecture Behavioral of LatchDD is
    signal Q1,Q2 : std_logic;
    begin
    -- Positive Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q2<='0';
    elsif(rising_edge(clk)) then Q2<=D;
    else null; end if;
    end process;
    -- Negative Edge ---
    process(D,clk,R)
    begin
    if R='1' then Q1<='0';
    elsif(falling_edge(clk)) then Q1<=D;
    else null; end if;
    end process;

    Q <= (Q1 or Q2);
    QN <= not(Q1 or Q2);

    end Behavioral;

    Hope this help you, I'm a student of vhdl, so plz don't be to harsh if
    this is not the answer



    On Feb 18, 2:18 am, wrote:
    > Hi,
    >
    > How many wait statements can we use in a process statement?
    > I us Quartus II web edition for compilation. On compiling my code it
    > says, we cant use multiple wait statements in the same process.
    > However many books give examples of processes with multiple wait
    > statements.
    >
    > I need to design a sample data transfer interface. For this i need to
    > find the clock events.
    > However i cannot use
    >
    > * if clk'EVENT and clk = '1' then *
    >
    > construct. What exactly i need is to wait till i get the next clock
    > edge. Hope you understood the question. Any solution to it, in logic
    > or code will be a great help for proceeding my project.
    >
    > Thanking You all in advance.
    > Lee
     
    R Quijano, Feb 19, 2007
    #4
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