VHDL

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comp.lang.vhdl
A
why registered output?
  • Alex
Replies
2
Views
15K
Chris Pruett
C
B
Why on Simulation the result is not what is expected?
  • b.g.dariush
Replies
3
Views
1K
goouse99
G
V
why not use std_logic_arith?
  • vu_5421
Replies
6
Views
3K
Mike Treseler
M
M
Why not use boolean all the time for synthesis?
  • me
Replies
19
Views
5K
me
M
R
Why no one ,no reply for this query??please reply me
Replies
2
Views
1K
[email protected]
R
J
Why MyHDL?
  • Jan Decaluwe
Replies
5
Views
1K
Mike Treseler
M
N
Why multiplex signals?
  • Neha
Replies
3
Views
2K
Neha
N
O
Why more area occupation for less logic usage ????
  • Oleg
Replies
3
Views
1K
Ralf Hildebrandt
R
T
Why isnt buffer used more often?
  • Tricky
Replies
9
Views
2K
Paul Uiterlinden
P
C
Why is this not a locally static choice?
  • Charles M. Elias
Replies
2
Views
2K
Charles M. Elias
C
Z
why is this code wrong? generic or others?
  • Zheyu.Gao
Replies
1
Views
704
Aiken
A
K
Why is this code persnickety?
  • KK6GM
Replies
7
Views
1K
KK6GM
K
F
Why is the last value used to detect the rising edge
  • fl
Replies
4
Views
1K
Andy
A
P
Why hardware designers should switch to Eclipse
  • Philippe
2
Replies
35
Views
3K
Nico Coesel
N
P
why FSM so big
  • Pasacco
Replies
4
Views
945
Pasacco
P
K
Why ever use std_logic_vector intead of signed/unsigned?
  • kevin.neilson
Replies
11
Views
2K
KJ
K
R
Why Doesn't VHDL Have a Wildcard Sensitivity List?
  • rickman
2 3
Replies
42
Views
5K
Mike Treseler
M
J
Why doesn't this work in an XC9572XL?
  • JohnDuq
Replies
4
Views
1K
JohnDuq
J
W
Why doesn't this situation generate a latch?
  • Weng Tianxiang
Replies
14
Views
2K
Martin Thompson
M
S
Why doesn't this produce the logic I expect?
  • Shannon
Replies
3
Views
1K
Andy
A
F
Why does this if process wrong?
  • fl
Replies
5
Views
898
Nicolas Matringe
N
T
why does std_logic_arith suck?
  • Toby
Replies
4
Views
2K
Mike Treseler
M
F
Why does Modelsim not display some signals?
  • fl
Replies
2
Views
1K
HT-Lab
H
N
Why do we hate variables?
  • Nicolas Matringe
Replies
4
Views
5K
fabbl
F
A
Why do VHDL gate level models simulate slower than verilog
  • abilash
Replies
1
Views
1K
Jim Lewis
J
T
Why do shared variables HAVE to be a protected type?
  • Tricky
Replies
5
Views
2K
Paul
P
T
Why cant protected types be elements in an array?
  • Tricky
Replies
3
Views
2K
Tricky
T
T
Why cant protected type methods have a parameter thats an access type?
  • Tricky
Replies
1
Views
1K
JimLewis
J
E
Why can't I do simuation?
  • ecenus
Replies
0
Views
6K
ecenus
E
R
why can not signal be assigned asscess type?
  • risingsunxy
Replies
0
Views
923
risingsunxy
R
C
Why are these signal inferred latches?
  • charles.elias
Replies
2
Views
1K
David Binnie
D
M
why am i getting incompatible error
  • MNQ
Replies
5
Views
3K
MNQ
M
F
Why a signal cannot control the file IO operation?
  • fl
Replies
1
Views
1K
Nicolas Matringe
N
W
Why 'a plurality of N' must be used for 'N' in patent claims
  • wtxwtx
Replies
11
Views
5K
soar2morrow
S
M
why "setup-time and hold-time"?
  • maazbecin
Replies
0
Views
4K
maazbecin
M
J
who is owner of this group?
  • JK
Replies
2
Views
769
james
J
R
Who is interested in taking the Synthworks' VHDL Testbenches and Verification Course?
Replies
0
Views
1K
[email protected]
R
T
Who can explain the bit'pos for me?
  • threeinchnail
Replies
6
Views
8K
D Stanford
D
M
white noise generator
  • MNQ
Replies
5
Views
6K
MNQ
M
S
While loop problems
  • seoken
Replies
1
Views
789
JohnDuq
J
J
while loop
  • jiten
Replies
17
Views
20K
Andy Peters
A
D
while condition
  • Daniel
Replies
7
Views
4K
Ralf Hildebrandt
R
B
While compiling
  • Be myself
Replies
2
Views
873
Tero Kapanen
T
G
Which VHDL Development Kit
  • g_loughnan
Replies
0
Views
1K
g_loughnan
G
F
Which version of VHDL supports delimited comments.
  • fl
Replies
3
Views
842
Tim McBrayer
T
H
Which Verification Methodologies Are You Using?
  • harrytheasicguy
Replies
1
Views
747
Nicholas Paul Collin Gloucester
N
P
which training is good java or embedded systems
  • pshallur
Replies
0
Views
752
pshallur
P
D
Which software from Xilinx
  • Davo
Replies
2
Views
2K
james
J
J
Which simulator buy? ModelSim or ActiveHDL?
  • jgauthier68
Replies
0
Views
832
jgauthier68
J
R
Which PSL is included in the VHDL-200X LRM sent to IEEE for approval?
  • Reuven
Replies
4
Views
1K
Colin Paul Gloster
C

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