Why does Modelsim not display some signals?

Discussion in 'VHDL' started by fl, Feb 25, 2013.

  1. fl

    fl Guest

    Hi,
    I use Xilinx ISE to run a small VHDL file. From Xilinx ISE goes to Modelsim in behaviour simulation (use the default do {hcic_tb.fdo} command), I find that thw waveform window does not display the following two signals:

    SIGNAL filter_out_addr : std_logic; -- boolean
    SIGNAL filter_out_done : std_logic; -- boolean

    while
    SIGNAL filter_out_rdenb : std_logic; -- boolean

    shows in the waveform window. What is the reason for display or not?

    Thanks


    .............
    testbench file:

    SIGNAL filter_out_rdenb : std_logic; -- boolean
    SIGNAL filter_out_addr : std_logic; -- boolean
    SIGNAL filter_out_done : std_logic; -- boolean

    la: filter_out_rdenb <= ce_out;

    filter_out_procedure (
    clk => clk,
    reset => reset,
    rdenb => filter_out_rdenb,
    addr => filter_out_addr,
    done => filter_out_done);
     
    fl, Feb 25, 2013
    #1
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  2. fl

    fl Guest

    It seems these two signals will display after I turn off optimization to vsim:

    -novopt

    My new question is that in testbench it is acceptable to test a point with signal? Why are they get optimized?
    Thanks,
     
    fl, Feb 25, 2013
    #2
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  3. fl

    HT-Lab Guest

    I would suggest you read up on the +acc switch in the user manual rather
    than using -novopt which turns off all optimisation. You can have full
    visibility + optimisation.

    Hans
    www.ht-lab.com
     
    HT-Lab, Feb 27, 2013
    #3
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