VHDL

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comp.lang.vhdl
P
What tools do you use ? Why ?
  • psihodelia
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7
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2K
Kim Enkovaara
K
H
What to do with "Unconnected output port" warnings?
  • Herb T
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1
Views
9K
Stephane
S
J
What to do when post-synthesis simulation do not pass
  • jasonL
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2
Views
935
jasonL
J
A
what this
  • Attila Csosz
Replies
1
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2K
Attila Csosz
A
R
What Simulators support PSL?
  • Reuven
Replies
3
Views
867
NigelE
N
A
What should I do next to simulation a project on kit?
  • Aoniti
Replies
1
Views
806
MM
M
W
What official function should I call to genertate a sum of products in VHDL
  • Weng Tianxiang
Replies
2
Views
840
Paul
P
N
what newsgroup software you use for this VHDL group ?
  • Nigel Noldsworth
Replies
4
Views
1K
Rich Webb
R
A
What is `transaction`event
  • Ash72
Replies
0
Views
376
Ash72
A
W
What is wrong with the following code?
  • willem oosthuizen
Replies
9
Views
4K
fe
F
W
what is wrong with my VHDL code? I am so dissappointed...
  • walala
Replies
3
Views
4K
Ralf Hildebrandt
R
S
what is wrong in this code
  • sridar
Replies
0
Views
633
sridar
S
M
What is use of filters??
  • maheshkumar0459
Replies
1
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2K
flymolo
F
W
What is the state of state machine after power-up without reset conditions
  • Weng Tianxiang
Replies
7
Views
2K
Mike Treseler
M
P
What is the purpose of the access system in VHDL:
  • parag_paul
Replies
2
Views
746
Paul Uiterlinden
P
G
What is the purpose of an Architecture Identifier?
  • Grant Robertson
Replies
4
Views
983
TigerJade
T
V
what is the problem with latch inference?
  • VHDL Guy
Replies
9
Views
14K
fp
F
W
What is the name of Altera latest and most advanced chip serial that is competable in technology wit
  • Weng Tianxiang
Replies
2
Views
1K
Weng Tianxiang
W
P
What is the meaning of a signal in VHDL
  • parag_paul
Replies
13
Views
4K
Mike Treseler
M
J
What is the meaning of "." in VHDL
  • jasonkee111
Replies
1
Views
1K
sridar
S
R
What is the difference of modelsim command run -continue and run -all
  • rxjwg98
Replies
2
Views
8K
KJ
K
F
What is the difference of "array (63 downto 0) of ...." and "array (0to 63) of ...."
  • fl
Replies
5
Views
1K
Andy
A
F
What is the difference between XX'image() and to_string()
  • fl
Replies
1
Views
987
Mike Treseler
M
P
what is the difference between the types std_logic and std_ulogic
  • parag_paul
Replies
5
Views
29K
vipinlal
V
Z
What is the difference between 'std_logic_vecotor' and 'signed'
  • Zhi
Replies
8
Views
3K
Zhi
Z
Z
What is the difference between 'std_logic_vecotor' and 'signed'
  • Zhi
Replies
2
Views
842
Ralf Hildebrandt
R
W
What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
  • wtxwtx
Replies
10
Views
4K
wtxwtx
W
F
What is the best way to generate 6 set 3-bit address
  • fl
Replies
2
Views
730
Andy
A
S
What is the best way to clock data in on one clock edge and out on another?
  • simon.stockton
Replies
4
Views
1K
Peter Alfke
P
W
What is the basis on flip-flops replaced by a latch
  • Weng Tianxiang
Replies
13
Views
4K
Weng Tianxiang
W
V
What is the base type?
  • Valentin Tihhomirov
Replies
3
Views
651
valtih1978
V
S
what is problem in this code....
  • sheri
Replies
2
Views
641
Brad Smallridge
B
M
What is meant by Static name
  • Mohammed A khader
Replies
2
Views
2K
Mohammed A khader
M
B
what is incorrect about my usage of array with port entity?
  • brian_farmer
Replies
5
Views
1K
Andy
A
P
what is difference between generate and for loop in vhdl
  • pravin.vhdl
Replies
0
Views
4K
pravin.vhdl
P
W
What is called carry chain structure in FPGA is called in IC?
  • Weng Tianxiang
Replies
6
Views
1K
glen herrmannsfeldt
G
V
What is a signal?
  • valtih1978
Replies
1
Views
705
rickman
R
V
what is a better approach to synthezise synchronous reset on FPGA?
  • valentin tihomirov
Replies
9
Views
3K
Ray Andraka
R
B
what is 'A=>0' ?
  • Boki
Replies
2
Views
806
boki
B
S
what is "Timing Score" in place & rout report
  • spartan
Replies
1
Views
2K
anupam
A
H
What is "ASIC turnkey service"?
  • Heelothere
Replies
0
Views
864
Heelothere
H
X
what happens if sensitivity of a combinatorial process is incomplete?
  • xohaibhassan
Replies
1
Views
3K
joris
J
J
what happened to opencores.org
  • James Dalton
Replies
8
Views
3K
am_y
A
C
What happened to comp.lang.vhdl on google?
  • charles.elias
Replies
2
Views
1K
dbtid
D
J
What graphical entry/documentation tools?
  • jamesp
Replies
4
Views
1K
Hans
H
R
What functions ?
  • RealInfo
Replies
2
Views
705
Tricky
T
T
What FSM should I use ?
  • Thor Phersen
2
Replies
22
Views
4K
Jan Decaluwe
J
A
What does what standard say about this:
  • Alvin Andries
Replies
4
Views
842
Jonathan Bromley
J
T
What does this VHDL code do???
  • thai.tony
Replies
3
Views
942
thai.tony
T
M
What does this Verilog code do?
  • mp_91
Replies
0
Views
940
mp_91
M

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