what is problem in this code....

[sheri]

hi all,
there is some problem in the following code which i could not figure
it out..I have synthesised this code in xilinx XST..The scehamtics
shown is wrong..So please help me to solve this..thanks in advance..

entity simple_design is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : out STD_LOGIC;

e : out STD_LOGIC);

end simple_design;



architecture Behavioral of simple_design is



procedure logic (

signal a : in std_logic;

signal b : in std_logic;

signal c : in std_logic;

signal x : out std_logic

) is

begin

x <= a and b and c;

end procedure logic;



begin



logic_P:

process (a, b, c)

begin

d <= a xor b xor c;

logic (

a => a,

b => b,

c => c,

x => e

);

end process logic_P;



end architecture Behavioral;

 

[jeppe]

Seems to work nicely at my computer (with ISE 9.1)

 

[Brad Smallridge]

I have synthesised this code in xilinx XST..The scehamtics

shown is wrong.

The RTL schematic shows three inputs A, B, and C with two
outputs D and E. What did you expect? );

Brad Smallridge
Ai Vision