VHDL

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comp.lang.vhdl
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"signal does not hold its value outside clock edge"
  • =?iso-8859-1?q?Guilherme_Corr=EAa?=
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ieee.numeric_std?
  • Weng Tianxiang
2
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24
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janeruth
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Variables Vs signals
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1
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Paul Uiterlinden
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generate statements
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1
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Egbert Molenkamp
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How to include don't care minterms
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3
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Modelsim Directory
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3
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Convert decimal number in binary number
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1
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Anders Hellerup Madsen
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ModelSim + Simulink VHDL Cosimulation
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3
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mubarak.mohmed
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Scoreboard and Checker in Testbench?
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16
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pini
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Designing a I2C slave using Spartan 3E and VHDL
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2
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Konstantin Schmidt
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latch warning...
  • Noah
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4
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Ralf Hildebrandt
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What are Weak Unknown, Weak Zero and Weak 1?
  • Kuan Zhou
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1
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Paul Uiterlinden
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How much time does it need to sort 1 million random 64-bit/32-bit integers?
  • Weng Tianxiang
2
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36
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Brannon
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Re: Is there an elegant way to set an unsigned vector to 1
  • Jan De Ceuster
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5
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Thomas Stanka
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can I run unix shell command in the ModelSim shell?
  • clinton__bill
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2
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Jonathan Bromley
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I2C bus multiplexing inside CPLD
  • Thomas
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10
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Nicolas Matringe
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Default value for an unconstrained port
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11
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Andy
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VHDL vs. Verilog
  • Pawel
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4
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Pawel
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Address decoding
  • Laurent Pinchart
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3
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Jim Lewis
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SRAM vs Cache
  • Michael
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4
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Mario Trams
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VHDL finite state machine
  • ekelly30
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11
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ekelly30
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regarding filters in vhdl
  • viswanath
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7
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kjaraline
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"Target of signal assignment is not a signal"
  • Nicolas Moreau
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9
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Andy
A
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String to std_logic_vector
  • Shannon
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10
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Shannon
S
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Combinational Loop?
  • ALuPin
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5
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Ken Smith
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Modelsim Library Problem
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6
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JohnDuq
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character to std_logic value
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3
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Mike Treseler
M
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FORMAL VERIFICATION USING CONFORMAL LEC ( CADENCE TOOL)
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5
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kitcha
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VHDL function synthesis
  • Thanga
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6
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KJ
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reading files in vhdl
  • paris
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4
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Sajan
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LFSR
  • Spartan815
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10
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VhdlCohen
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Target type ieee.std_logic_1164.std_ulogic in signal assignment isdifferent frim expression type std
  • Diego UTN-FRP
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4
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Diego UTN-FRP
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VHDL Case Statement
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0
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The Hath
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LSFR
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8
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Kholdoun TORKI
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VHDL implementation of SPI for MAX6675
  • tarek
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8
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cosmin
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best VHDL book
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4
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Symon
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where to use CPLD & where to use FPGA?
  • kulkarku
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6
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kulkarku
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Verilog 2's Complement Shifter
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4
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sharp
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overflow with signed and unsigned values
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2
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Egbert Molenkamp
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bidirectional connection between two bidirectional ports
  • Manfred Balik
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12
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Marc Guardiani
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NCSIM simulator
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1
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Eyck Jentzsch
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Enum type as array range
  • rickman
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1
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Mike Treseler
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74xx series TTL library avaliable?
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6
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Andy
A
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Writing a binary output file
  • Fredxx
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9
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Fredxx
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Hexadecimal to Binary File Conversion Utility
  • Victor Hannak
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0
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Victor Hannak
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two-dimensional array, assign to zero, vhdl
  • --MMS--
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8
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Andy
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is there any way to convert modelsim wave output to text file?
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9
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Divyang M
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type conversation problems
  • Olaf Petzold
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2
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Ajeetha
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ASIC RTL and FPGA RTL
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One-hot Coding of State machines
  • Clyde R. Shappee
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Wallclimber
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