I just wanted to dump the values at a time and then advance the
simulation time(when i know there is no major activity going on) and
then re run the simulation form the advanced time in order to save
some simulation time.
Oh dear... very strange assumptions here!
If there is truly *no* activity, then advancing simulation time
is FREE and consumes essentially no simulator CPU! VHDL simulation
is event-driven. If there is no scheduled activity for the
next (let's say) 1us of simulated time, then the only thing the
simulator needs to do is to add 1us to the current time (NOW) and
then do whatever the next scheduled event may be. All the
simulation activity takes place in delta cycles; making time
progress costs nothing.
On the other hand, as others have pointed out, if there is *any*
activity then you *must* simulate it because you can't predict
what its effects are going to be.
If you are so sure about the state of the system after your long
period of time, then why not use the simulator's command-line
"force" command to put the entire sim into that state and then
re-start simulation? The absolute value of simulated time will
be wrong, but otherwise everything will be set up the way you
want it. Personally, though, I wouldn't trust myself to be
able to force the sim into a future state with sufficient
accuracy.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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