ASIC to FPGA porting/migrating

[sundar]

Hi all,

Currently I am working on porting an ASIC piece of VHDL code in to
FPGA.

Please share your inputs on " Points to be noted" while migrating ASIC
to FPGA.
I am new to this activity and trying to collect materials relevant to
this and proceed accordingly.

Also I found few info on some topics in the groups but not exactly
suiting my requirements.

Thanks in advance,
Sundar

 

[tarmopalm]

Hi,

If your Target Device is FPGA from Xilinx, then I would look following
Link:

http://www.xilinx.com/support/training/rel/asic-user-rel.htm

Tarmo

 

[Kim Enkovaara]

Currently I am working on porting an ASIC piece of VHDL code in to
FPGA.

Please share your inputs on " Points to be noted" while migrating ASIC
to FPGA.
I am new to this activity and trying to collect materials relevant to
this and proceed accordingly.

The biggest obstacle might be the amount of clock domains and clock
gating in the asic. fpgas are quite restricted in terms of clocking
resources and some asic designs might be hard to transfer to fpga
because of that.

Also of course you need to migrate all the memories from asic ones
to fpga ones. It's easiest for fpga to use inferrable memories that
have generics to tell their size. This might not work for some exotic
memory configurations tough. Also if you have exotic >2 port memories
in asic you might be in trouble. CAM memories are problematic with
fpgas if you use them etc.

Also if the asic uses very deep logic it might be problematic to map
into fpga. In asic it's still feasible to use 30+ levels of logic at
some points, but with fpga that is hard to get working with reasonable
clock frequency.

The question is very large, and very dependent on the design. And the
age of the design also. Some very old asic designs can also contain
parts which are made in vhdl, but from pure gates and with some
asynchronous tricks and they might be really hard to get working in
a fpga.

--Kim

 

[sundar]

The biggest obstacle might be the amount of clock domains and clock
gating in the asic. fpgas are quite restricted in terms of clocking
resources and some asic designs might be hard to transfer to fpga
because of that.

Also of course you need to migrate all the memories from asic ones
to fpga ones. It's easiest for fpga to use inferrable memories that
have generics to tell their size. This might not work for some exotic
memory configurations tough. Also if you have exotic >2 port memories
in asic you might be in trouble. CAM memories are problematic with
fpgas if you use them etc.

Also if the asic uses very deep logic it might be problematic to map
into fpga. In asic it's still feasible to use 30+ levels of logic at
some points, but with fpga that is hard to get working with reasonable
clock frequency.

The question is very large, and very dependent on the design. And the
age of the design also. Some very old asic designs can also contain
parts which are made in vhdl, but from pure gates and with some
asynchronous tricks and they might be really hard to get working in
a fpga.

--Kim

Thanks Tarmo and Kim for your responses.....
as kim mentioned it is mostly depended on case to case basis
also is there any protoyping tool or methodology available for this???

 

[sundar]

Dear all,

During this process of prototyping ASIC to FPGA I have encountered
basic issues.
I have some NEC rams memory files which I believe are part of the ASIC
cell libraries.
I need to convert these files to FPGA equivalent. Any suggestions?

I am using synplify-premier for my implementation.

Thanks in advance,
Sundar

 

[gabor]

Dear all,

During this process of prototyping ASIC to FPGA I have encountered
basic issues.
I have some NEC rams memory files which I believe are part of the ASIC
cell libraries.
I need to convert these files to FPGA equivalent. Any suggestions?

I am using synplify-premier for my implementation.

Thanks in advance,
Sundar

You still haven't mentioned which FPGA vendor, but if it is Xilinx,
the best bet is to look in the Libraries Guide for the standard
inference templates for block RAMs or distributed RAMs depending
on what you're trying to do. It's also worthwhile to see what
the embedded memory in your FPGA is capable of. For example in
Xilinx the block memories are all registered, so if you try to
infer asynchronous memory you'll generate a pile of fabric logic
instead of a block RAM.

 

[sundar]

You still haven't mentioned which FPGA vendor, but if it is Xilinx,
the best bet is to look in the Libraries Guide for the standard
inference templates for block RAMs or distributed RAMs depending
on what you're trying to do.  It's also worthwhile to see what
the embedded memory in your FPGA is capable of.  For example in
Xilinx the block memories are all registered, so if you try to
infer asynchronous memory you'll generate a pile of fabric logic
instead of a block RAM.

Thanks for the prompt response....i am using xilinx vendor and i will
now hunt in to Coregen to find equivalent memory
thanks for your tip
apart from that any suggestions on removing synopsys library for
existing ASIC design????