Ben Cohen's "The VHDL training package"

[apple]

I have these books. It appears as if "The VHDL Training Package" is a
collection
of notes...

The preface says "intended as a set of training notes for a VHDL
training class and are intended to be used in conjunction with the
following books:

Real chip design and verification using verilog and VHDL
component design by example
VHDL coding styles and methodologies
VHDL answers to frequently asked questions



But there is no order mentioned. Which book to read first? All at
once? Are there instructions somewhere on how to use this training
package?

 

[d_s_klein]

I have these books.  It appears as if "The VHDL Training Package" is a
collection
of notes...

The preface says "intended as a set of training notes for a VHDL
training class and are intended to be used in conjunction with the
following books:

Real chip design and verification using verilog and VHDL
component design by example
VHDL coding styles and methodologies
VHDL answers to frequently asked questions

But there is no order mentioned.  Which book to read first?  All at
once?  Are there instructions somewhere on how to use this training
package?

Mr. Cohen's books are well written and valuable, but I recommend this
book for the beginner:

<http://www.amazon.com/Students-Guide-Second-Systems-Silicon/dp/
1558608656/ref=sr_ob_2?ie=UTF8&s=books&qid=1277227480&sr=1-2>

RK

 

[apple]

Mr. Cohen's books are well written and valuable, but I recommend this
book for the beginner:

I've been reading the "beginner" books for a few years. I am
comfortable with VHDL, although not with styles or methods.

the Ben Cohen training package looks to be very well written, but I
don't understand which comes first. Read them in sequence, together,
constantly cross reference, or what?

What happened to Ben Cohen?

the books mention http://www.vhdlcohen.com/, and they were published
2002. The webpage no longer exists. I don't see any recent posts on
this newsgroup made by him.

 

[Jonathan Bromley]

What happened to Ben Cohen?

the books mention http://www.vhdlcohen.com/, and they were published
2002. The webpage no longer exists. I don't see any recent posts on
this newsgroup made by him.

He seems to have relocated to http://systemverilog.us/
where it says that he has teamed up with
Stu Sutherland for training.

 

[HT-Lab]

I've been reading the "beginner" books for a few years. I am
comfortable with VHDL, although not with styles or methods.

the Ben Cohen training package looks to be very well written, but I
don't understand which comes first. Read them in sequence, together,
constantly cross reference, or what?

What happened to Ben Cohen?

the books mention http://www.vhdlcohen.com/, and they were published
2002. The webpage no longer exists. I don't see any recent posts on
this newsgroup made by him.

Have a look at the verificationguild and search for his *comments* on VHDL.

http://verificationguild.com/

Hans
www.ht-lab.com

 

[d_s_klein]

I've been reading the "beginner" books for a few years.  I am
comfortable with VHDL, although not with styles or methods.

the Ben Cohen training package looks to be very well written, but I
don't understand which comes first.  Read them in sequence, together,
constantly cross reference, or what?

What happened to Ben Cohen?

the books mentionhttp://www.vhdlcohen.com/, and they were published
2002.  The webpage no longer exists.  I don't see any recent posts on
this newsgroup made by him.

Ashenden also has advanced books, you may consider those.

For "styles and methods" Cohen's 'VHDL Coding Styles and
Methodologies' was useful to me. I question the value of reading all
the others.

RK

 

[SystemVerilog]

Ben Cohen status & "The VHDL Training Package"

I have these books. It appears as if "The VHDL Training Package" is a
collection of notes..

This was really a set of training notes handed during a training VHDL class. The notes were bound into a booklet. Since then, I migrated into the world of Verilog, SystemVerilog and with emphasis on assertions with PSL, and then SVA, and then VMM. In terms of books:

* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
Addesses the practical use of assertions with SystemVerilog, but can co-exist with VDHL using the "bind" to bind SystemVerilog code to VHDL code.

* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
Using VMM for verification

* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
I recomend the use of SVA over PSL. SVA is superior in features.

* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
Good book that teaches design techniques using VDL and Verilog.

* Component Design by Example, 2001 ISBN 0-9705394-0-1
Book show s how to write specification requirements, and demonstrates the flow in the design process. I do not like the approach I used in the verification where text command files were used for the definition of transactions. This is a passe technique.

* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
Address the VHDL language

* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
Addresses some advanced topics.
--------------------------------------------------------------------------
Ben Cohen (831) 345-1759
[systemverilog dot us ben at systemverilog dot us